Abstract: The present disclosure relates to a graphene spin transistor for all-electrical operation at room temperature and a logic gate using the graphene Rashba spin transistor. A graphene spin transistor of the present disclosure provides a graphene spin FET (Field Effect Transistor) for all-electrical operation at room temperature without a magnetic field or a ferromagnetic electrode by utilizing the Rashba-Edelstein effect in the graphene or the spin Hall effect of a TMDC (Transition Metal Dichalcogenide) material in order to replace CMOS transistors and extend Moore's Law, and further provides a logic gate using the graphene Rashba spin transistor.

Abstract: An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type.

Abstract: An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.

Abstract: The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.

Abstract: The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode structure is in mirror symmetry with a second electrode structure with respect to the P-type heavily doped region 24, and active regions of the N-type well 60 and 62 are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and 26.

Abstract: An ion implanted region is formed by implanting Mg ions into a predetermined region of the surface of the first p-type layer. Subsequently, a second n-type layer is formed on the first p-type layer and the ion implanted region. A trench is formed by dry etching a predetermined region of the surface of the second n-type layer until reaching the first n-type layer. Next, heat treatment is performed to diffuse Mg. Thus, a p-type impurity region is formed in a region with a predetermined depth from the surface of the first n-type layer below the ion implanted region. Since the trench is formed before the heat treatment, Mg is not diffused laterally beyond the trench. Therefore, the width of the p-type impurity region is almost the same as the width of the first p-type layer divided by the trench.

Abstract: An insulated gate bipolar transistor and a fabrication method therefor, wherein the fabrication method for the insulated gate bipolar transistor comprises the following steps: implanting hydrogen ions, arsenic ions, or nitrogen ions into a substrate from a back surface of the insulated gate bipolar transistor so as to form an n-type heavily doped layer (202) of a reverse conduction diode, the reverse conduction diode being a reverse conduction diode built into the insulated gate bipolar transistor. The described fabrication method and the obtained insulated gate bipolar transistor from a recombination center in an n+ junction of the reverse conduction diode, thereby accelerating the reverse recovery speed of the built-in reverse conduction diode, shortening the reverse recovery time thereof, and improving the performance of the insulated gate bipolar transistor.

Abstract: Semiconductor structure and a method for fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate, a doped source layer formed in the substrate; a channel pillar formed on the doped source layer; a gate structure formed on the sidewall surface of the channel pillar; a first contact layer, having a first thickness and formed at the surface of the doped source layer; and a second contact layer having a second thickness and formed on the top surface of the channel pillar. The first thickness is greater than the second thickness.

Abstract: A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.

Abstract: Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: The present invention relates to a method for assembling molecules on the surface of a two-dimensional material formed on a substrate, the method comprises: forming a spacer layer comprising at least one of an electrically insulating compound or a semiconductor compound on the surface of the two-dimensional material, depositing molecules on the spacer layer, annealing the substrate with spacer layer and the molecules at an elevated temperature for an annealing time duration, wherein the temperature and annealing time are such that at least a portion of the molecules are allowed to diffuse through the spacer layer towards the surface of the two-dimensional material to assemble on the surface of the two-dimensional material. The invention also relates to an electronic device.

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

Abstract: We disclose herein a gate controlled bipolar semiconductor device comprising: a collector region of a first conductivity type; a drift region of a second conductivity type located over the collector region; a body region of a first conductivity type located over the drift region; a plurality of first contact regions of a second conductivity type located above the body region and having a higher doping concentration than the body region; a second contact region of a first conductivity type located laterally adjacent to the plurality of first contact regions, the second contact region having a higher doping concentration than the body region; at least two active trenches each extending from a surface into the drift region; an emitter trench extending from the surface into the drift region; wherein each first contact region adjoins an active trench so that, in use, a channel is formed along said each active trench and within the body region; wherein the second contact region adjoins the emitter trench; and where

Abstract: According to the embodiment of the invention, the semiconductor device includes a semiconductor member, a first electrode, a second electrode, a third electrode, a first conductive member, and a first insulating member. The first semiconductor member includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The second semiconductor region includes one of a first material and a second material. The third semiconductor region is provided between at least a part of the first semiconductor region and the second semiconductor region. The first electrode is electrically connected with the first semiconductor region. The second electrode is electrically connected with the second semiconductor region. At least a part of the third semiconductor region is between an other portion of the third electrode and the first conductive member. At least a part of the first insulating member is between the third electrode and the semiconductor member.

Abstract: A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation.

Abstract: The disclosure provides a superjunction IGBT (insulated gate bipolar transistor) device, wherein a carrier storage layer of a first conductivity type is provided between a voltage sustaining layer and a base region, and a MISFET (metal-insulator-semiconductor field effect transistor) of a second conductivity type is also integrated in a cell, with at least one gate of the MISFET is connected to the emitter contact thereof. The MISFET is turned off at a low forward conduction voltage, helping to reduce the conduction voltage drop. The MISFET can provide a path for carriers of a second conductivity type and prevent the carrier storage layer from suffering a high electric field when the forward conduction voltage is slightly higher or it is at the forward blocking state, helping to improve the reliability.

Abstract: A semiconductor structure includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor device, a doped isolation region, and at least one isolation pillar. The substrate includes a core layer and a composite material layer, the semiconductor epitaxial layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor epitaxial layer. The first semiconductor device is disposed on the substrate, where the first semiconductor device includes a first semiconductor cap layer disposed on the semiconductor barrier layer. The doped isolation region is disposed at one side of the first semiconductor device. At least a portion of the isolation pillar is disposed in the doped isolation region, and the isolation pillar surrounds at least a portion of the first semiconductor device and penetrates the composite material layer.