Abstract: A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer is formed. A second isolation insulating layer made of different material than the first isolation insulating layer is formed so that a first upper portion of the fin structure is exposed. A dummy gate structure is formed over the exposed first upper portion of the first fin structure. The second isolation insulating layer is etched by using the dummy gate structure as an etching mask. The dummy gate structure is removed so that a gate space is formed. The second isolation insulating layer is etched in the gate space so that a second upper portion of the fin structure is exposed from the first isolation insulating layer. A gate dielectric layer and a gate electrode layer are formed over the exposed second portion of the fin structure.

Abstract: There is provided an image module package including a substrate, a photo sensor chip, a molded transparent layer and a glass filter. The substrate has an upper surface. The photo sensor chip is attached to the upper surface of the substrate and electrically connected to the substrate. The molded transparent layer covers the photo sensor chip and a part of the upper surface of the substrate, wherein a top surface of the molded transparent layer is formed with a receptacle opposite to the photo sensor chip. The glass filter is accommodated in the receptacle.

Abstract: A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.

Abstract: A photo sensor, a manufacturing method thereof, and a display panel are disclosed. By an ion implantation method forming an N-type region and a P-type region on a surface of polycrystalline silicon in a same layer respectively, compatibility with an ion implantation process is ensured, while covering a layer of an amorphous silicon photosensitive layer on the polycrystalline silicon enhances light absorption ability and can increase photo-generated electron-hole pairs. Furthermore, built-in electric fields exist on a horizontal direction and a vertical direction, which can more effectively separate the electron-hole pairs to enhance photo-generated electric current to improve accuracy of fingerprint recognition.

Abstract: An integrated circuit (IC) includes: a first cell including an input pin and an output pin extending in a first direction; a second cell adjacent to the first cell in the first direction and including an input pin and an output pin extending in the first direction; a first cell isolation layer extending between the first cell and the second cell in a second direction crossing the first direction; and a first wire extending in the first direction, overlapping the first cell isolation layer, and being connected to the output pin of the first cell and the input pin of the second cell, wherein the output pin of the first cell, the input pin of the second cell, and the first wire are formed in a first conductive layer as a first pattern extending in the first direction.

Abstract: An image sensing device is disclosed. The image sensing device includes a pixel array including a plurality of unit pixels, each of which is configured to generate a pixel signal in response to incident light.

Abstract: A high k passivation layer, an anti-reflective coating layer, and a buffer layer are disposed over semiconductor substrate including photodiodes formed therein. Trenches are etched into the semiconductor substrate through the buffer layer, anti-reflective coating layer, and the high k passivation layer in a grid-like pattern surrounding each of the photodiodes in the semiconductor substrate. Another high k passivation layer lines an interior of the trenches in the semiconductor substrate. An adhesive and barrier layer is deposited over the high k passivation layer that lines the interior of the trenches. A deep trench isolation (DTI) structure is formed with conductive material deposited into the trenches over the adhesive and barrier layer to fill the trenches. A grid structure is formed over the DTI structure and above a plane of the buffer layer. The grid structure is formed with the conductive material.

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Abstract: A die attachment to a support is disclosed. In an embodiment, a semiconductor package includes a support and a die attached to the support by an adhesive on a backside of the die, wherein the die includes a capacitive pressure sensor integrated on a CMOS read-out circuit, and wherein the adhesive covers only a part of the backside of the die.

Abstract: A plurality of capacitors and a holding body constructed to hold the plurality of capacitors. Each of the plurality of capacitors includes a semiconductor substrate, a first electrode layer, a dielectric layer, a second electrode layer, and an outer electrode. Among a first capacitor and a second capacitor of the plurality of capacitors, the second capacitor has a shape different from a shape of the first capacitor in at least one of the first electrode layer, the second electrode layer, and the outer electrode.

Abstract: A semiconductor device is provided. The semiconductor device comprises an inductor in a far back end of line layer and a capacitor adjacent to and electrically coupled with the inductor. The capacitor comprises a first electrode layer arranged over sidewalls and a bottom surface of a via in a first insulating layer A dielectric layer is provided over the first electrode layer. A second electrode layer is provided over the dielectric layer and a metal fill layer is provided over the second electrode layer. The metal fill layer has a top surface at least level with a top surface of the first insulating layer.

Abstract: A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-? metal gate disposed over the first set of fins, and a second high-? metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.

Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a photodiode.

Abstract: An IC structure includes first and second cell rows extending in a first direction. The first cell row includes first cells each including one or more first fins having first source/drain regions of a first conductivity type and one or more second fins having second source/drain regions of a second conductivity type opposite the first conductivity type. The second cell row includes second cells each including one or more third fins having third source/drain regions of the first conductivity type and one or more fourth fins having fourth source/drain regions of the second conductivity type. The first cells have a same first number of the one or more first fins, and the second cells have a same second number of the one or more third fins less than the first number of the one or more first fins.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

Abstract: A first gate structure, a second gate structure, and a third gate structure each extend in a first direction. A first gate via is disposed on the first gate structure. The first gate via has a first size. A second gate via is disposed on the second gate structure. The second gate via has a second size that is greater than the first size. A third gate via is disposed on the third gate structure. The third gate via has a third size that is less than the second size but greater than the first size. A first source contact is disposed adjacent to a first side of the first gate via. A first drain contact is disposed adjacent to a second side of the first gate via opposite the first side. A second drain contact is disposed adjacent to a first side of the third gate via.

Abstract: To prevent peeling at an interface between layers forming a layer structure of a solid-state imaging element even in a case where stress is caused by an increase in pressure in a cavity in a configuration in which a translucent member is provided on the solid-state imaging element with a support portion interposed therebetween and the cavity is formed between the solid-state imaging element and the translucent member.

Abstract: A display device includes a base, an organic light-emitting element including a stacked structure that has a first electrode layer, an organic light-emitting layer, and a second electrode layer that are stacked in order on the base, a drive element that is provided on the base, and drives the organic light-emitting element, and an auxiliary electrode layer provided on the base, and including an end surface that is in contact with the second electrode layer.