Abstract: A display apparatus includes an organic light emitting display panel including a thin film encapsulation layer, a first conductive layer directly on the thin film encapsulation layer, at least one inorganic layer on the thin film encapsulation layer and having a density of about 2.05 g/cm3 to about 2.4 g/cm3, and a window on the at least one inorganic layer. In the display apparatus according to embodiments of the present disclosure, the generation of bubbles may be suppressed or reduced.

Abstract: A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.

Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface opposed to each other, and a porous metal oxide film on a side of the first main surface of the semiconductor substrate, the porous metal oxide film having a plurality of pores. The semiconductor substrate has a connection electrically connected to the porous metal oxide film, and the semiconductor substrate is configured to provide a power supply path from the second main surface to the connection on the first main surface.

Abstract: A photoelectric converter According to an embodiment of the present disclosure includes: an organic photoelectric conversion section; an inorganic photoelectric conversion section; and an optical filter. The organic photoelectric conversion section includes a first electrode, a second electrode, and an organic photoelectric conversion layer. The first electrode includes one electrode and another electrode. The second electrode is disposed to be opposed to the first electrode. The organic photoelectric conversion layer is disposed between the first electrode and the second electrode and is electrically coupled to the one electrode. The organic photoelectric conversion layer and the other electrode are provided with an insulation layer therebetween. The inorganic photoelectric conversion section has the first electrode disposed between the inorganic photoelectric conversion section and the organic photoelectric conversion section.

Abstract: A semiconductor device includes a first region, a second region, a third region, and a fourth region. The first region includes a first portion of an N-well and a plurality of P-type transistors formed over the first portion of the N-well. The first region extends in a first direction. The second region includes a first portion of a P-well and a plurality of N-type transistors formed over the first portion of the P-well. The second region extends in the first direction. The third region includes a second portion of the P-well. The fourth region includes a second portion of the N-well. The first region and the second region are disposed between the third region and the fourth region.

Abstract: An optoelectronic device includes a LED that is suited to the emission of a radiation and that includes an active layer, and a conversion layer that extends over the active layer of the LED and that includes a plurality of fluorophores suited to the conversion of the radiation emitted by the LED, wherein the conversion layer is confined laterally by a mirror reflecting both the radiation converted by the fluorophores and the radiation not converted by the fluorophores, and vertically between a first and a second multilayer reflective filters forming a resonant Fabry-Perot cavity that blocks the radiation not converted by the fluorophores and has a transmittance peak for the radiation converted by the fluorophores.

Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

Abstract: In some embodiments, the present disclosure relates to an image sensor structure. The image sensor structure includes a substrate. The substrate includes a first side and a second side opposite the first side. A photodetector extends into the first side of the substrate. An isolation structure comprises a first isolation segment and a second isolation segment that extend through the substrate. The first isolation segment and the second isolation segment are respectively on opposite sides of the photodetector and comprise a dielectric. A first metal line is on the first side of the substrate. A dummy contact structure comprises a first dummy segment and a second dummy segment. Both the first dummy segment and the second dummy segment comprise metal and extend from the first metal line to the first isolation segment and the second isolation segment, respectively.

Abstract: Methods for inserting dummy boundary cells in an integrated circuit (IC) are provided. A plurality of macros and a top channel are merged into floorplan of the IC. The top channel is arranged between the macros and is filled with a plurality of first dummy boundary cells, and each of the macros includes a macro boundary and a main pattern surrounded by the macro boundary. The first dummy boundary cells within the top channel and between a first macro and a second macro are replaced with a plurality of second dummy boundary cells. The macro boundaries of the first and second macros are formed by the second dummy boundary cells. First gate length of dummy patterns within the first dummy boundary cells is greater than second gate length of dummy patterns within the second dummy boundary cells. The first and second dummy boundary cells are the same size.

Abstract: An optoelectronic device (LV) with a reflective composite material (V) having a carrier (1) consisting of aluminium, having an interlayer (2) composed of aluminium oxide present on one side (A) of the carrier (1) and having a reflection-boosting optically active multilayer system (3) that has been applied via the interlayer (2). The interlayer (2) consisting of aluminium oxide has a thickness (D2) in the range from 5 nm to 200 nm and that, on the opposite side (B) of the carrier (1) from the reflection-boosting optically active multilayer system (3), a superficial layer (9) of a metal or metal alloy having, at 25° C., a specific electrical resistivity of not more than 1.2*10?1 ?mm2/m has been applied. The thickness (D9) of the superficially applied layer (9) is in the range from 10 nm to 5.0 ?m.

Abstract: The present disclosure provides a semiconductor device with a T-shaped buried gate electrode and a method for forming the semiconductor device. The semiconductor device includes a semiconductor substrate having an active region, and a first gate electrode disposed in the semiconductor substrate. The semiconductor device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the first gate electrode. The first gate electrode has a first portion extending across the active region and a second portion extending into the first source/drain region.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.

Abstract: An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.

Abstract: Provided is a method of manufacturing a DRAM. A plurality of openings are formed in the substrate. A hard mask is formed on the sidewall of an upper part of each opening. The substrate and the hard mask are partially removed to form a plurality of isolation trenches and to define active regions. Each active region is located between the isolation trenches and remaining portions of the hard mask are located on two sides of each active region. The isolation trenches and the openings are filled with a dielectric layer. The substrate and the dielectric layer are partially removed to form a plurality of buried word line trenches. Each buried word line trench extends along a third direction and passes through the active regions, the openings and the isolation trenches. A plurality of buried word lines are formed in the buried word line trenches.

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

Abstract: A semiconductor device includes: a first electrode; a second electrode; and a multi-layered stack including a hafnium oxide layer of a tetragonal crystal structure which is positioned between the first electrode and the second electrode, wherein the multi-layered stack includes: a seed layer for promoting tetragonal crystallization of the hafnium oxide layer and having a tetragonal crystal structure; and a booster layer for boosting a dielectric constant of the hafnium oxide layer.

Abstract: A pixel unit and a manufacturing method thereof, a sensor, and a sensor array are provided. The pixel unit comprises: a photosensitive unit, configured to generate a photo-generated carrier according to received radiation; at least two transmission units, connected between the photosensitive unit and at least two floating diffusion nodes, and configured to transfer the photo-generated carrier from the photosensitive unit to the at least two floating diffusion nodes; and the at least two floating diffusion nodes, configured to store and output the photo-generated carrier generated by the photosensitive unit. Among the at least two floating diffusion nodes, the floating diffusion node spaced by more transmission units from the photosensitive unit has a lower electric potential.

Abstract: A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.

Abstract: In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.