Abstract: A method for equalizing capacities of electric storage devices that are connected in series in an electric storage device assembly charged and discharged by a charger/discharger includes charging/discharging the electric storage device assembly at a charging/discharging rate of 1 C or lower, individually measuring voltages of the electric storage devices, respectively, determining whether a time rate of change in voltage of one electric storage device of the electric storage devices has reached a time-rate-of-change reference value and then a time rate of change in voltage of another electric storage device of the electric storage devices has reached the time-rate-of-change reference value, and individually discharging, based on a determining result, the electric storage device by a discharging circuit provided separately from the discharger.

Abstract: A method for performing redundancy identification in an integrated circuit design. An optimized gate in a logic circuit is identified. A first netlist with a representation of the logic circuit is generated. An error is induced on the optimized gate. A second netlist is generated from a copy of the first netlist incorporating changes based on the error. Fan-out boundaries of the logic circuit are propagated for the first and second netlists. A redundancy report representing optimization steps performed to obtain the original logic circuit is analyzed to identify which steps are adequate to cause unobservability of the optimized gate. This is done by representing the optimization steps as constraints over the first and second netlists. Responsive to the error becoming undetectable under the constraints derived from the redundancy report, a minimal set of reductions is identified from the first netlist as the reason for unobservability of the optimized gate.

Abstract: Antenna array calibration for wireless charging is disclosed. A wireless charging system is provided and configured to calibrate antenna elements in a wireless charging station based on a feedback signal provided by a wireless charging device. The antenna elements in the wireless charging station transmit wireless radio frequency (RF) charging signals to the wireless charging device. The wireless charging device provides the feedback signal to the wireless charging station to indicate total RF power in the wireless RF charging signals. The wireless charging station is configured to adjust transmitter phases associated with the antenna elements based on the feedback signal until the total RF power in the wireless RF charging signals is maximized. By calibrating the antenna elements based on the feedback signal, it is possible to achieve phase coherency among the antenna elements without requiring factory calibration.

Abstract: An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.

Abstract: Provided is a method for controlling charging in a mobile terminal. The method includes, applying a voltage to a charger upon detecting a connection to the charger via a cable; transmitting a signal for requesting charging to the charger, and switching a charging mode; and charging a power that is received from the charger according to the switched charging mode.

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Abstract: An on-board control apparatus has a power generation means that has a communication part; a storage battery that is chargeable by receiving electric power from the power generation means; a control means that is configured to be communicatable with the communication part and controls charging of the storage battery; and a state-of-charge measurement means that measures a state of charge of the storage battery. The control means transmits a signal that is to prohibit charging the storage battery to the communication part when an ignition of a vehicle is turned off, and the state-of-charge measurement means measures the state of charge of the storage battery, during a period of time in which charging the storage battery is prohibited, after the ignition of the vehicle is turned off.

Abstract: A system and method of performing physical synthesis of a chip design are described. The method includes performing a baseline physical synthesis to determine a timing slack associated with each device, the timing slack indicating a margin by which timing requirements for the associated device are exceeded, determining that a threshold has been exceeded, the determining based on an analysis of a histogram of the timing slack, and executing a stage-by-stage physical synthesis based on determining that the threshold has been exceeded. The executing the stage-by-stage physical synthesis includes running a stage of the stage-by-stage physical synthesis to determine real timing slack, mapping the real timing slack to virtual timing slack, and running a next stage of the stage-by-stage physical synthesis using the virtual timing slack.

Abstract: A system and method of performing physical synthesis of a chip design are described. The method includes performing a baseline physical synthesis to determine a timing slack associated with each device, the timing slack indicating a margin by which timing requirements for the associated device are exceeded, determining that a threshold has been exceeded, the determining based on an analysis of a histogram of the timing slack, and executing a stage-by-stage physical synthesis based on determining that the threshold has been exceeded. The executing the stage-by-stage physical synthesis includes running a stage of the stage-by-stage physical synthesis to determine real timing slack, mapping the real timing slack to virtual timing slack, and running a next stage of the stage-by-stage physical synthesis using the virtual timing slack.

Abstract: A circuit design system includes a simulator that determines an average charging current provided by each current insertion point in a cell and an average charging current along a path in the cell between a reference pin position and a candidate pin position. A candidate pin placement tester updates the average charging current along the path by adding the average charging current of each insertion point to the average charging current along the path to produce an updated average charging current along the path and uses the updated average charging current along the path to determine a time to failure for the cell.

Abstract: Techniques for circuit concurrent gate sizing and repeater insertion considering the issue of size conflicts are described herein. Certain of these techniques can be directed to coupled gates within levels of a levelized circuit falling within a coupling window defined by a minimum slack gate and adjacent gates coupled to the minimum slack gate with an adjacency parameter less than a predefined adjacency limit.

Abstract: This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.

Abstract: A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.

Abstract: In a position measuring method, a mask including first patterns to be transferred and second patterns not to be transferred is prepared. The position coordinates of the second patterns are measured with a position measuring apparatus and an inspection system. First position correction data is generated based on the position coordinates of the second patterns. A difference is obtained between the measured position coordinates of the second patterns and the first position correction data is corrected using the obtained difference. Second position correction data is generated from the corrected first position correction data. An optical image including the position coordinates of the first and second patterns is acquired. The position coordinates of the first patterns of the optical image are corrected using a difference between the position coordinates of the second patterns of the optical image and of the second patterns based on the second position correction data.

Abstract: Simulators are linked to a circuit design tool by establishing a plurality of simulator objects in response to a plurality of registration commands, respectively. Each registration command specifies a simulation interface application associated with one of the simulators, and the simulation interface application has procedures for initiating functions of the associated simulator. For each simulator, values of properties of the simulator are stored in the respective simulator object. The values of the properties include references to the procedures of the associated simulation interface application. An interface, which is responsive to input commands, accesses the values of the properties and executes the procedures referenced by the values of the properties to initiate the functions of the simulators.

Abstract: Systems and techniques for using a three-dimension (3D) resist profile aware etch-bias model are described. A 3D resist profile aware etch-bias model can be calibrated based on empirical data. Next, the 3D resist profile aware etch-bias model can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.

Abstract: A wireless power transmission apparatus for high efficiency energy charging, includes a resonator configured to transmit power, and a power supply unit configured to supply power to the resonator. The apparatus further includes a first switching unit configured to connect the resonator to the power supply unit, and disconnect the resonator from the power supply unit, and a controller configured to control the first switching unit based on an amount of current flowing into the resonator.

Abstract: Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components may be duplicated into the one or more duplicated electronic design components. One or more CDC effect models are automatically injected into the representation by adding the one or more CDC effect models along one or more paths in the representation. Proof results are generated at least via proving or disproving one or more checkers for the electronic design by verifying or simulating the representation with the one or more CDC effect models that are automatically injected into the representation.

Abstract: A charging and discharging system of a vehicle storage device utilizes a buffer device adapted for voltage adjustment toward a charging voltage of a charging device on the vehicle, and also for adjusting the charging current, in such a way that the charging voltage and current from the charging device may be reduced in advance for charging the storage device. With the charging and discharging system, storage device using lithium ion battery cell may be adapted to various vehicle system.