Abstract: A computer-implemented method for filtering components from a logical component hierarchy is provided. The method uses a computing device having a processor and a memory. The method includes identifying, in the memory, a filter associated with the logical component hierarchy. The method also includes comparing, by the processor, a sub-component of the logical component hierarchy with the filter. The method further includes identifying the sub-component for filtration based on the comparison of the sub-component with the filter. The method also includes filtering the sub-component from the logical component hierarchy.

Abstract: A method of checking joule heating of an integrated circuit design, the method includes dividing the integrated circuit design into a plurality of windows, determining a power index of each window, adjusting the specification current value associated with each of the corresponding windows, and generating a current violation report, by a processor, of the integrated circuit. Each window includes one or more circuit elements. Each circuit element is associated with a corresponding current value. Each window is associated with a corresponding specification current value. Each power index is associated with a corresponding window. An amount of adjustment of the specification current value is a function of the power index of each corresponding window. The current violation report includes one or more entries. Each entry is associated with at least a corresponding window and one or more corresponding current values which exceed the corresponding adjusted specification current value.

Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.

Abstract: System and method of automatically performing flip-flop insertions for each net in a logic interface by using the RTL-estimated maximum count as a limit. Based on the timing analysis on the physical layout, a flip-flop insertion count needed for each net is derived and candidate locations for insertions are automatically detected. A set of constraints is applied to identify ineligible locations for flip-flop insertions. If more flip-flop insertions than the count limit are needed to satisfy the timing requirements for a net, timing-related variables are iteratively adjusted using the current layout until the timing requirements can be satisfied using the RTL count limit. If all the nets in the interface need fewer flip-flop insertions than the RTL count limit, the information can be fed back to update the RTL count limit. Each net is then parsed and flip-flops are inserted at appropriated locations.

Abstract: A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).

Abstract: An apparatus for controlling a battery pack and an energy storage system including the apparatus are disclosed. In one embodiment, the battery pack includes at least one battery tray each including one or more battery cells. The apparatus may include an open circuit voltage (OCV) calculator and a state of charge (SOC) estimator. The OCV calculator may receive OCV measurement values of the battery cells of each battery tray when the power of the battery pack is turned on, and calculate a final OCV of the battery cells based at least in part on the OCV measurement values. The SOC estimator may extract an SOC value corresponding to the final OCV from an SOC table and estimate the extracted SOC value as an initial SOC.

Abstract: A voltaic cell comprising an iron in alkali anode where metal iron is oxidized to iron II hydroxide and a ferricyanide in alkali cathode where ferricyanide is reduced to ferrocyanide, and uses thereof.

Abstract: A method for achieving clock timing closure in an integrated circuit (IC) design includes designing an IC using one or more component cells selected from a cell library to produce the design. A timing analysis of the design is performed to determine if timing constraints are satisfied. When a given time constraint is not satisfied, a component cell selected from the cell library is replaced with a replacement cell that has the same function and the same footprint as the replaced component cell, but has a different timing characteristic based on the phase relationship of the signal being capacitively coupled to enhance the likelihood of meeting the given time constraint. The timing analysis is repeated with the replacement cell. The process of replacing component cells and performing timing analysis may be iterative.

Abstract: A computer implemented method of mask decomposition and optimization for directed self assembly (DSA) which includes: inputting design information of an integrated circuit that is to be patterned using a DSA process; mapping the design information into a tree graph comprising nodes and edges; searching the tree graph to identify a longest path through the tree graph; identifying a branch comprising an edge on the tree graph not on the longest path and stemming from one of the nodes on the longest path; outputting the one node on the longest path that connects to the branch as a hot spot; and modifying a photomask by removing the branch from the photomask; wherein the method is performed by one or more computing devices.

Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Abstract: A method being performed by a processor includes, acquiring data of patterns of a plurality of cells that include an identified pattern for which an evaluation value of an optical image falls outside a first allowable range among patterns in which each a pattern being single cell alone, creating the pattern of a mask by arranging the patterns of the plurality of cells that include the identified pattern, and evaluating an optical image of the identified pattern in the created pattern of the mask.

Abstract: A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler classes, each filler class having a set of filler cells, is classified that are configured to fill the gaps depending on a design requirement. Then, a filler insertion pattern based on a required ratio is identified such that horizontal and vertical density of the set of filler classes in the circuit layout are as per the required ratio and the cell row of the circuit layout has at least one filler cell from each of the set of filler classes.

Abstract: A modular wireless charging assembly is presented herein. In particular, the charging assembly comprises a plurality of wireless charging pads or bases disposed in removably interconnected relation with one another to provide a collective charging surface or interface. Particularly, each of the wireless charging pads or bases include a charging surface which is structured and configured to wirelessly charge an electronic device (e.g., a cellular telephone, mp3 player, PDA, game console, etc.) disposed thereon. The various wireless charging pads or bases include attachment assemblies which are structured to dispose adjacent wireless charging pads or bases in a removably interconnected relation with one another.

Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.

Abstract: Dynamic systems may require a large number of coils (charging pads) which may be installed into the roadway to wirelessly provide power to electric vehicles as they are traveling along the roadway. The current in each of these coils may need to be turned on and off as a vehicle drives over the coils in order to efficiently utilize power and properly convey power to the passing vehicles. The supply network behind these coils may need to be capable of managing the individual coils with minimal infrastructure and cost as well as be capable of distributing the required power from the power grid to these pads efficiently and safely. The supply network may include charging coils, switches, local controllers, and distribution circuitry within a modular element, which may receive power from external sources and may be controlled by a central controller.

Abstract: A power charging apparatus and a battery apparatus quickly charge a battery with power by separately charging each battery cell with power. The power charging apparatus includes: a power supplier supplying power; and a charging part having at least two chargers corresponding one-to-one to at least two battery cells connected to each other in parallel, each of the at least two chargers charging the corresponding battery cell with power transmitted from the power supplying unit. The battery apparatus includes: a battery having at least two battery cells connected to each other in parallel; and a charging part having at least two chargers corresponding one-to-one to the at least two battery cells and charging the at least two chargers with power received.

Abstract: A method, system, and computer program product to perform dynamic voltage frequency scaling of an integrated circuit include performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage. Obtaining a canonical model expressing timing slack at each test location of the integrated circuit is as a function of one or more sources of variability, one of the one or more sources of variability being voltage, and performing the dynamic voltage-frequency scaling based on selecting at least one of a clock period and the voltage using the canonical model.

Abstract: In an approach for predicting a process fail limit for a semiconductor manufacturing process, a computer determines a potential working process condition for each of a plurality of process parameters varied in forming a test wafer feature. The computer determines a process sigma value for each of the plurality of process parameters in forming the test wafer feature and a measurement sigma value. The computer evaluates a set of measurements of the test wafer feature compared to an acceptable wafer feature dimension, where each measurement of the set of measurements is a pass or fail as compared to the acceptable wafer feature dimension. The computer determines whether one or more fails are evaluated compared to the acceptable wafer feature dimension. The computer produces a predicted process fail limit based, at least in part, on the evaluation of fails, the measurement sigma value, and a desired target sigma value.

Abstract: Methods and systems for designing a binary spatial filter based on data indicative of a desired exposure condition to be emulated by an inspection system, and for implementing the binary spatial filter in an optical path of the inspection system, thereby enabling emulation of the desired exposure condition by interacting a light beam of the inspection system with the binary spatial filter. The present method and systems enable on-the-fly and on-demand design and implementation/generation of spatial filters for use in inspection systems.