Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller may sense a first threshold voltage of the selected memory cell. In response to the sensed first threshold voltage being between a first pre-program verify level and a first program verify level, the controller may bias the selected memory cell to a first voltage level. The first pre-program verify level might be less than a final pre-program verify level and the first program verify level might be less than a final program verify level.

Abstract: A phase-change memory device and a dynamic resistance drift compensation method thereof are provided. The phase-change memory device includes a plurality of bit lines; a plurality of source lines crossing the plurality of bit lines; a plurality of memory cells at respective intersections between the plurality of bit lines and the plurality of source lines, the plurality of memory cells each including a phase-change layer; a current generator connected to the plurality of bit lines and configured to generate a set current to be supplied to each of the plurality of memory cells; and a control driver configured to control the current generator and the plurality of bit lines to supply the set current to each of the plurality of memory cells.

Abstract: A memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including a plurality of program loops. Each of the plurality of program loops includes a program pulse application operation and a verify operation. The control logic controls the peripheral circuit to store cell status information and apply a program limit voltage. The control logic sets a verify pass reference and applies the program limit voltage determined based on the cell status information.

Abstract: Provided herein is a page buffer, a semiconductor memory device with the page buffer, and a method of operating the semiconductor memory device. The page buffer includes a plurality of data latch components coupled to a sensing node, a bit line controller coupled between a bit line and the sensing node, the bit line controller configured to control a node value of the sensing node based on a program state of a memory cell that is coupled to the bit line during a program verify operation, and a sub-latch component configured to latch verification data based on the node value during the program verify operation, wherein each data latch component sets the node value to a first logic value when a program state that corresponds to program data has a threshold voltage distribution that is higher than that in a target program state during the program verify operation.

Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines connected to the array of memory cells, a plurality of data lines connected to the array of memory cells, a plurality of shield lines, and control logic. The plurality of shield lines might be interleaved with the plurality of data lines. The control logic might be configured to implement a program verify operation of respective memory cells of the array of memory cells connected to a selected access line including charging the plurality of shield lines to a first voltage level, discharging the plurality of shield lines to a voltage level less than the first voltage level, and sensing a voltage level on each data line to determine whether each respective memory cell coupled to the selected access line has been programmed to a target level for the respective memory cell.

Abstract: A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, the first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected t

Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

Abstract: Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor.

Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.

Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

Abstract: In certain aspects, a circuit for power leakage blocking can include a voltage generation circuit that includes an amplifier connected at a negative input to a reference voltage and providing an output to a gate of a first transistor. A drain voltage of the first transistor can be fed back to a positive input of the amplifier. The voltage generation circuit can receive a first voltage at a source of the first transistor. The voltage generation circuit can supply a second voltage at a drain of the first transistor. The circuit can further include a pair of transistors. The pair of transistors can include a second transistor and a third transistor. Respective bulks of the pair of transistors can be connected to a bulk of the first transistor. The gates of the pair of transistors can be controlled according to a comparison between the first voltage and the second voltage, such that only one of the pair of transistors is on at a time.

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test.

Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.

Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.

Abstract: Code comparators with nonpolar dynamical switches are provided. An example apparatus comprises: a plurality of row wires; a plurality of column wires; one or more cross-point devices, and a nonpolar volatile two-terminal device formed within a plurality of cross-point devices. Each cross-point device in the plurality of cross-point devices is located at a cross-point between a row in the plurality of row wires and a column in the plurality of column wires; the nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device. The nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device.