Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.

Abstract: A semiconductor storage device includes: a plurality of first memory cells; a word line connected to gates of the first memory cells; a voltage generation circuit configured to generate voltage to be supplied to the word line on the basis of a set value; and a control unit configured to execute a write sequence that includes a plurality of loops, each loop including a program operation to increase a threshold voltage of at least part of the first memory cells to thereby write data to the first memory cells and a verify operation to verify the data written to the first memory cells. The voltage generation circuit generates voltage to be supplied to the word line at start of the verify operation on the basis of a first set value, and the control unit adjusts the first set value in accordance with progress of the write sequence.

Abstract: Described are systems and methods for performing memory programming operations in the overwrite mode. An example memory device includes: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: responsive to identifying a first data item to be stored by a portion of the memory array, causing a first memory programming operation to be performed to program, to a first target threshold voltage, a set of memory cells included by the portion of the memory array; and responsive to identifying a second data item to be stored by the portion of the memory array, causing a second memory programming operation to be performed to program the set of memory cells to a second target threshold voltage exceeding the first target threshold voltage.

Abstract: In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows, bit lines respectively coupled to the columns, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row based on a current data page. Each memory cell is configured to store a piece of N-bits data at one of 2N levels, where N is an integer greater than 1. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, one multipurpose storage unit, and N?1 data storage units.

Abstract: An initial level of sensing voltage is set based on one or more characteristics of the segment of the memory device. A count for operational cycles for a segment of a memory device is set. Responsive to determining that a number of operational cycles performed on the segment of the memory device has reached the set count of operational cycles, the sensing voltage is varied with respect to the initial level of sensing voltage. The sensing voltage is adjusted to a new level based on wearing of the segment of the memory device during the number of operational cycles performed on the segment of the memory device.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell and a first boosting circuit. The first boosting circuit generates a first voltage, a second voltage, and a third voltage lower than the second voltage at a first output terminal. The first, second and third voltages is used for a write operation. The write operation includes a first program operation and a first verify operation executed after the first program operation. The first boosting circuit generates the first voltage at the first output terminal during the first program operation, generates the third voltage at the first output terminal at end of the first program operation, generates the second voltage at the first output terminal during the first verify operation, and then generates the first voltage to the first output terminal during the first verify operation.

Abstract: A semiconductor memory device includes: first conductive layers; second conductive layers; a first semiconductor layer disposed between the first conductive layers and the second conductive layers; a charge storage layer that includes a first part disposed between the plurality of first conductive layers and the first semiconductor layer and a second part disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor memory device is configured such that a read operation and a first operation performed before the read operation are performable. In the first operation: a first voltage is supplied to the first wiring; and a second voltage smaller than the first voltage is supplied to an n-th second conductive layer counted from the one side in the first direction.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

Abstract: A memory device includes a cell wafer having a first pad on one surface thereof; and a peripheral wafer bonded to the one surface of the cell wafer, and having a second pad coupled to the first pad. The cell wafer includes a memory cell array; first and second bit lines coupled to the memory cell array; and a bit line selection circuit configured to couple one of the first and second bit lines to the first pad. The peripheral wafer includes a page buffer low-voltage circuit including a first page buffer low-voltage unit corresponding to the first bit line and a second page buffer low-voltage unit corresponding to the second bit line; and a page buffer high-voltage circuit configured to couple one of the first and second page buffer low-voltage units to the second pad.

Abstract: A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.

Abstract: A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor. The peripheral circuit performs a read operation on a selected memory cell among the plurality of memory cells. The peripheral circuit is configured to read data that is stored in the selected memory cell by applying a read voltage to a selected word line among word lines that are connected to the plurality of memory cells and by applying a pass voltage to unselected word lines, and configured to transmit a boosting prevention voltage to a channel region in the cell string while applying an equalizing voltage to the word lines.

Abstract: According to one embodiment, a memory system includes: a memory device to store data; and a controller to control an operation for the memory device. The memory device executes a program operation by a first program voltage on memory cells belonging to a first address of the memory device; detect at least one first memory cell among the memory cells by using a first determination level and a second determination level different from the first determination level, the at least one first memory cell having a threshold voltage of a value different from a value between the first determination level and the second determination level; and generate unique information of the memory device, based on a position of the first memory cell in the first address.

Abstract: ABSTRACT A semiconductor memory device provides a first memory cell array including a plurality of first memory blocks, a second memory cell array comprising a plurality of second memory blocks, and a voltage supply line electrically connected to the plurality of first memory blocks and the plurality of second memory blocks. Moreover, this semiconductor memory device is configured to execute a write operation. At a first timing of this write operation, the voltage supply line is not electrically continuous with the first and second memory blocks. Moreover, a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first and second memory blocks is larger than a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first memory block.

Abstract: Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

Abstract: A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.

Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block.

Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.