Abstract: An electronic device includes a display panel, a first optical part, and a second optical part including a diffraction optical element having a diffraction grating. The display panel include a first display area for displaying a first image having a first color, a second display area disposed adjacent to the first display area to display a second image having a second color different from the first color, and a third display area disposed adjacent to the second display area to display a third image having a third color different from the first color and the second color.

Abstract: A method for manufacturing a device comprising a membrane extending over a useful cavity, the method comprising: providing a generic structure comprising a surface layer extending in a main plane and arranged on a first face of a support substrate, the support substrate comprising elementary cavities opening under the surface layer and partitions delimiting each elementary cavity, the partitions having top surfaces that form all or part of the first face of the support substrate; defining a group of adjacent elementary cavities, such that a contour of the group of elementary cavities corresponds, in the main plane, to a contour of the useful cavity; and removing the partitions situated within the contour of the group of elementary cavities, in order to form the useful cavity, and to free the surface layer arranged above the useful cavity and forming the membrane.

Abstract: A semiconductor package assembly includes a semiconductor package that includes a semiconductor chip bonded to a substrate. The assembly also includes a plurality of passive devices mounted on a bottom surface of the substrate opposite the semiconductor chip, the plurality of passive devices including a plurality of operable passive devices and a plurality of standoff passive devices, wherein a height of each of the plurality of standoff passive devices is greater than a height of any of the plurality of operable passive devices. The assembly also includes a plurality of solder structures attached to the bottom surface of the substrate. When mounted on a circuit board, the standoff passive devices prevent solder bridging.

Abstract: Described herein is an electronic component that may include a substrate, wherein the substrate may include at least two electrodes, wherein the at least two electrodes are each spaced apart from each other on and/or within the substrate. When the electronic component is in a first operating state, an electrolytic material may be disposed at least in a spatial region between the at least two electrodes, wherein the electrolytic material comprises at least one polymerizable material. When the electronic device is in a second operating state, at least one electrical connection may be made between the at least two electrodes, wherein the at least one electrical connection comprises an electrically conductive polymer. The electrically conductive polymer may comprise one or more fiber structures, wherein the one or more fiber structures are in physical contact with the at least two electrodes.

Abstract: A first electrode (110) has optical transparency, and a second electrode (130) has light reflectivity. An organic layer (120) is located between the first electrode (110) and the second electrode (130). Light-transmitting regions (a second region (104) and a third region (106)) are located between a plurality of light-emitting units (140). An insulating film (150) defines the light-emitting units (140) and includes tapers (152, 154). A sealing member (170) covers the light-emitting units (140) and the insulating film (150). A low reflection film (190) is located on the side opposite to a substrate (100) with the second electrode (130) therebetween. The low reflection film (190) covers at least one portion of the tapers (152 and 154).

Abstract: Examples of a substrate processing apparatus includes a chamber, an upper cover provided inside the chamber, an electrostatic chuck which includes an annular portion of a dielectric body and an embedded electrode embedded into the annular portion, the electrostatic chuck being provided inside the chamber, and a plasma unit configured to generate plasma in a region below the upper cover and the electrostatic chuck, wherein the annular portion includes an annular first upper surface located immediately below the upper cover, and a second upper surface located immediately below the upper cover and surrounding the first upper surface, the second upper surface having a height higher than a height of the first upper surface.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

Abstract: A method for forming a double-sided capacitor structure includes: providing a base, the base including a substrate, a plurality of capacitor contacts located in the substrate, a stack structure located on a surface of the substrate and a plurality of capacitor holes running through the stack structure and exposing the capacitor contacts, the stack structure including sacrificial layers and support layers which are stacked alternately; successively forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; forming a first conductive filling layer in the capacitor holes; forming an auxiliary layer for sealing the capacitor holes; removing a part of the auxiliary layers and several of the support layers and the sacrificial layers to expose the first electrode layer; and, forming a second dielectric layer and a third electrode layer.

Abstract: A substrate processing apparatus that includes a substrate holder, a cup member, an elevating mechanism, a first nozzle, and a camera. The substrate holder holds a substrate and rotates the substrate. The cup member surrounds the outer circumference of the substrate holder. The elevating mechanism moves up the cup member so that the upper end portion of the cup member is located at the upper end position higher than the substrate held by the substrate holder. The first nozzle has a discharge port at a position lower than the upper end position, and discharges first processing liquid from the discharge port to an end portion of the substrate. The camera images an imaging region that includes the first processing liquid discharged from the discharge port of the first nozzle and is viewed from an imaging position above the substrate.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.

Abstract: Disclosed is an electroluminescent display device including a first pixel including a first sub pixel configured to emit first colored light, a second sub pixel configured to emit second colored light, and a third sub pixel configured to emit third colored light, a first electrode in the first sub pixel, an emission layer on the first electrode, a second electrode on the emission layer, and a first charge blocking layer provided below the second electrode and configured to prevent a light emission in the emission layer, wherein the first electrode is electrically connected with a driving thin film transistor in a first contact area provided in the first sub pixel, and the first charge blocking layer is overlapped with the first contact area.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.

Abstract: The present disclosure discloses an evaporation method, an evaporation mask assembly, a display panel and a display device, which can reduce the complexity of the manufacturing process of the display panel and improve the yield of the display panel. The evaporation method may comprise: performing a first evaporation on a base substrate by using a first mask to form a first evaporation sub-pattern on the base substrate, wherein the first mask has a first opening area; and performing a second evaporation on the base substrate by using a second mask to form a second evaporation sub-pattern on the base substrate, wherein the second mask has a second opening area; wherein the combination of the first and second evaporation sub-patterns forms an evaporation pattern.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

Abstract: A system and method for fabricating on-die metal-insulator-metal capacitors capable of supporting relatively high voltage applications and increasing capacitance per area are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets such as two different power rails, two different control signals, or two different data signals. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. In high voltage regions, a MIM capacitor has one or more intermediate metal plates formed as floating plates between electrode metal plates. The floating plates have no connection to any power supply reference voltage level used by the integrated circuit.

Abstract: A capacitor structure and a method of preparing the same are provided. The method includes the followings. A substrate is provided. A stacked layer is formed on the substrate. A plurality of first via holes penetrating through the stacked layer are formed. The first via hole is filled with a conductive material to form a conductive pillar. A plurality of second via holes penetrating through the stacked layer are formed at a preset radius with the conductive pillar as an axis. The second via hole surrounds the conductive pillar circumferentially. The second via hole is filled with the conductive material to form an annular top electrode with a second gear.