Abstract: An organic light-emitting display device includes: a substrate; a pixel electrode on the substrate; an auxiliary electrode spaced apart from the pixel electrode; a first insulating film between the pixel electrode and the auxiliary electrode and covering an end of the pixel electrode and an end of the auxiliary electrode; an intermediate layer on the pixel electrode and including an emission layer; an opposite electrode covering the intermediate layer and contacting the auxiliary electrode; and a passivation layer covering the opposite electrode.

Abstract: The present application relates to semiconductor structure and forming method comprising: forming substrate, wherein plurality of capacitive contacts are provided in the substrate, plurality of electrically conductive contact pads are provided at surface of the substrate to be correspondingly connected to plurality of capacitive contacts on one-to-one basis, and a space is present between every two adjacent electrically conductive contact pads; forming filling layer that is fully filled in the space; forming stacked structure at the filling layer and surface of the electrically conductive contact pads, wherein the stacked structure includes plurality of supporting layers stacked one-on-another along direction perpendicular to the substrate, the filling layer is in contact with the supporting layer disposed at bottom of the stacked structure, and etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than preset value; and etching the stacked structure to for

Abstract: Microwave packaging uses signal vias and interposers, such as metal lead frame interposers. For example, the microwave circuit die includes signal vias that electrically connect the top side and the bottom side of the die. Microwave signal circuitry on the die have signal paths that are electrically connected to the top side of the signal vias. The microwave signal circuitry typically may have an operating frequency of 300 MHz or faster. The bottom side of the signal vias are electrically connected to corresponding areas on the top side of the interposer. The bottom side of the die may also include a ground plane, with ground vias that electrically connect the top side of the die to the ground plane.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. A pixel region is provided with a light emission function layer on a base substrate of the display substrate, and a separation region is provided with at least one first barrier structure. The first barrier structure includes a stopper pattern and a first separation component. A side surface of the first separation component has a recess, and a portion of the light emission function layer extending to the separation region is disconnected on the side of the first separation component. The separation region is provided with an inorganic layer structure on the base substrate. The inorganic layer structure includes multiple stacked inorganic film layers, the stopper pattern is located between two adjacent inorganic film layers and the first separation component is located on a side of the inorganic layer structure away from the base substrate.

Abstract: A semiconductor device includes a target layer disposed on a substrate, and a crack sensor for detecting a crack generated in the target layer. The crack sensor includes a first conductive pattern positioned at a bottom surface of the target layer, a second conductive pattern positioned on a top surface of the target layer, the top surface being opposite to the bottom surface of the target layer, a plurality of resistors, and nodes. The plurality of resistors are connected in parallel to each other through the first conductive pattern and the second conductive pattern. Each of the plurality of resistors is disposed to substantially penetrate the target layer.

Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: Methods and systems for implementing artificial intelligence enabled preparation end-pointing are disclosed. An example method at least includes obtaining an image of a surface of a sample, the sample including a plurality of features, analyzing the image to determine whether an end point has been reached, the end point based on a feature of interest out of the plurality of features observable in the image, and based on the end point not being reached, removing a layer of material from the surface of the sample.

Abstract: The present application discloses a semiconductor device with a horizontally arranged capacitor. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

Abstract: A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.

Abstract: The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.

Abstract: Resistive switching devices that contain lithium, including resistive switching devices containing a lithium titanate, and associated systems and methods are generally described. In some cases, the resistive switching device contains a lithium titanate-containing domain, a first electrode, and a second electrode. In some cases, the application of an electrical potential to the resistive switching device causes a change in resistance state of the lithium titanate-containing domain. The resistive switching devices described herein may be useful as memristors, and in applications that include Resistive-random access memory and neuromorphic computing.

Abstract: A reflective mask blank for EUV lithography includes: a substrate; a multilayer reflective film for reflecting EUV light; and a phase shift film for shifting a phase of EUV light, the multilayer reflective film and the phase shift film formed on or above the substrate in this order. The phase shift film includes a layer 1 including ruthenium (Ru) and at least one selected from the group consisting of oxygen (O) and nitrogen (N). Among diffraction peaks derived from the phase shift film observed at 2?: from 20° to 50° by out-of-plane XRD method, a peak having the highest intensity has a half value width FWHM of 1.0° or more.

Abstract: A circuit module includes a first wiring substrate having a first main surface and a plurality of first components mounted on the first main surface. The plurality of first components includes a multilayer component formed as a single chip by being sealed using resin members. The multilayer component includes a second wiring substrate having a second main surface and a third main surface that face each other, a second component mounted on the second main surface, and a third component mounted on the third main surface.

Abstract: A method for making a quantum device including: forming, over a semiconductor layer, a graphoepitaxy guide forming a cavity with a lateral dimension that is a multiple of a period of self-assembly of a di-block copolymer into lamellas; first deposition of the copolymer in the cavity; first self-assembly of the copolymer, forming a first alternating arrangement of first lamellas and of second lamellas; removal of the first lamellas; implantation of dopants in portions of the semiconductor layer previously covered with the first lamellas; removal of the second lamellas; second deposition of the copolymer in the cavity, over a gate material; second self-assembly of the copolymer, forming a second alternating arrangement of first and second lamellas; removal of the second lamellas; etching of portions of the gate material previously covered with the second lamellas.

Abstract: Image sensors are provided. The image sensors may include a substrate including first, second, third and fourth regions, a first photoelectric conversion element in the first region, a second photoelectric conversion element in the second region, a third photoelectric conversion element in the third region, a fourth photoelectric conversion element in the fourth region, a first microlens at least partially overlapping both the first and second photoelectric conversion elements, and a second microlens at least partially overlapping both the third and fourth photoelectric conversion elements. The image sensors may also include a floating diffusion region and first, second and third pixel transistors configured to perform different functions from each other. Each of the first, second and third pixel transistors may be disposed in at least one of first, second, third and fourth pixel regions. The first pixel transistor may include multiple first pixel transistors.

Abstract: A substrate for semiconductor module includes a plurality of insulating layers sequentially stacked on one another, N signal lines transmitting N signals respectively, the N signal lines having N vias that at least partially penetrate through the plurality of insulating layers and are arranged in an N-sided polygon shape in a plan view, and a capacitor element configured to provide capacitive coupling between the N signal lines, the capacitor element having a first coupling element that provides capacitive coupling between first and second vias adjacent to each other among the N vias and a second coupling element that provides capacitive coupling between third and fourth vias that are not adjacent to each other among the N vias.

Abstract: A constraint for a sensor assembly includes a silicon wafer and a flexible structure. The silicon wafer has a first side, a second side opposite to the first side, and a passageway extending through the silicon wafer from the first side to the second side. The first side is a continuous planar surface except for the passageway. The flexible structure extends from the second side.