Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.

Abstract: A semiconductor device includes a plurality of wirings (WR11) which are formed in the same layer above a semiconductor substrate, and a plurality of wirings (WR12) which are formed in the same layer as that of the plurality of wirings (WR11). The plurality of wirings (WR11) are extended in an X axis direction and arranged at a pitch (PT11) in a Y axis direction intersecting with the X axis direction when seen in a plan view, and the plurality of wirings (WR12) are extended in the X axis direction and arranged at a pitch (PT12) in the Y axis direction when seen in a plan view. The plurality of wirings (WR11) are electrically connected to the plurality of wirings (WR12), and the pitch (PT11) is smaller than the pitch (PT12).

Abstract: A power MOSFET includes a substrate, a semiconductor layer, a first gate, a second gate, a thermal oxide layer, a first CVD oxide layer, and a gate oxide layer. The semiconductor layer is formed on the substrate and has at least one trench. The first gate is located inside the trench. The second gate is located inside the trench on the first gate, wherein the second gate has a first portion and a second portion, and the second portion is located between the semiconductor layer and the first portion. The thermal oxide layer is located between the first gate and the semiconductor layer. The first CVD oxide layer is located between the first gate and the second gate. The gate oxide layer is generally located between the second gate and the semiconductor layer.

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Abstract: An apparatus and method for creating nanometric delta doped layers in epitaxial diamond includes providing a dummy gas load with gas impedance equivalent to the reactor, and switching gas supplied between the reactor and the gas dummy load without stopping either flow, thereby enabling rapid flow and rapid gas switching without turbulence. An atomically smooth, undamaged substrate can be prepared, preferably in the (100) plane, by etching the surface after polishing to remove subsurface damage. A gas phase chemical getter reactant such as hydrogen disulfide can be used to suppress incorporation of residual boron into the intrinsic layers. Embodiments can produce interfaces between doped and mobile layers that provide at least 100 cm2/Vsec carrier mobility and 1013 cm?2 sheet carrier concentration.

Abstract: A method of forming a self-forming barrier includes selectively removing a portion of a semiconductor dielectric layer to form a three-dimensional pattern within a remaining portion of the dielectric layer. A metal liner layer is disposed on a surface of the pattern to provide a metal lined pattern. A metal filling is disposed over the metal lined pattern, the metal filling being at least partially composed of a metal used in the metal liner layer. Diffusion ions are disposed in one of the metal filling and the metal liner layer. Heat is applied to the metal filling and metal liner layer to diffuse the diffusion ions from one of the metal filling and the metal liner layer into the dielectric layer to form a barrier layer between the metal liner layer and the dielectric layer.

Abstract: A display device including: a substrate configured to include a first region and a second region formed at an outer periphery of the first region; an emission layer disposed on the first region and the second region of the substrate; a polarizer disposed on the emission layer; a touch panel disposed on the polarizer; a window disposed on the touch panel; and a light blocking layer covering side surfaces of the polarizer and the touch panel and a top surface of the emission layer disposed on the second region of the substrate. The polarizer and the touch panel cover the first region of the substrate and expose the second region of the substrate.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.

Abstract: A scale-like portion wherein metal plating is changed into a scale-like form is provided by continuously carrying out laser spot irradiation on a lead frame, the front surface of which is coated with the metal plating. The scale-like portion is disposed in an optional portion of the lead frame, for example, in the vicinity of a gate break mark, in an outer peripheral portion in a region sealed with a molding resin, or around a semiconductor element. The adhesion between the lead frame and the molding resin improves owing to the anchor effect of the scale-like portion, and it is thus possible to suppress the molding resin separating from the lead frame.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess. The second surface is opposite to the first surface. The recess passes through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer over the second surface. The semiconductor device structure includes a first bonding pad in the recess and extending to the first wiring layer so as to be electrically connected to the first wiring layer. The semiconductor device structure includes a nickel layer over the first bonding pad. The semiconductor device structure includes a gold layer over the nickel layer.

Abstract: It is aimed to reduce a current concentration at the edge of the contact electrode. Provided is a semiconductor device including a semiconductor layer, a first trench electrode formed in the semiconductor layer on a front surface side thereof, and a second trench electrode formed in the semiconductor layer on the front surface side thereof so as to oppose the first trench electrode. Here, the first trench electrode is formed in a mesh-like pattern. The semiconductor layer may further include a first-conductivity-type region and a second-conductivity-type region having a different conductivity type than the first-conductivity-type region. The first trench electrode may be electrically connected to the first-conductivity-type region, and the second trench electrode may be electrically connected to the second-conductivity-type region.

Abstract: Provided are methods for synthesizing a halogen-functionalized carbon material and for fabricating an electronic device employing the same. The synthesizing method of the halogen-functionalized carbon material may include thermally treating a transition metal material at a first temperature in a hydrogen atmosphere and thermally treating the transition metal material at a second temperature, which is lower than or equal to the first temperature, while further supplying halocarbon on the transition metal material.

Abstract: A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.

Abstract: A display module includes abase substrate including an upper surface and a lower surface opposite the upper surface; a pixel layer facing the base substrate such that the upper surface of the base substrate is between the lower surface and the pixel layer, the pixel layer including a plurality of pixels; and a window member facing the base substrate such that the pixel layer is between the window member and the base substrate, the window member in an upper surface exposed to an outside thereof and a lower surface opposite the upper surface, and the upper surface of the window member and the lower surface of the base substrate include intaglio patterns, the intaglio patterns are overlapping with a dotted area when viewed in a plan view, and the display module is configured to be torn along the dotted area when a force is applied thereto.

Abstract: Provided is a metal film forming method which can form a metal film having excellent adhesion industrially advantageously and a metal film formed by using the method. A method of forming a metal film on a base includes an atomization step of atomizing a raw-material solution into a mist, in which the raw-material is prepared by dissolving or dispersing a metal in an organic solvent containing an oxidant, a chelating agent, or a protonic acid; a carrier-gas supply step of supplying a carrier gas to the mist; a mist supply step of supplying the mist onto the base using the carrier gas; and a metal-film formation step of forming the metal film on part or all of a surface of the base to causing the mist to thermally react.

Abstract: An adhesive film of the present invention includes a base material layer and a self-peeling adhesive layer laminated therein. The base material layer has a thermal contraction percentage in a direction of flow (thermal contraction percentage in an MD direction) and a thermal contraction percentage in an orthogonal direction with respect to the direction of flow (thermal contraction percentage in a TD direction) that satisfy the following conditions: (1) after heating at 150° C. for 30 minutes, 0.4?|thermal contraction percentage in MD direction/thermal contraction percentage in TD direction|?2.5 and average of thermal contraction percentage in MD direction and thermal contraction percentage in TD direction?2%, and (2) after heating at 200° C. for 10 minutes, 0.4?|thermal contraction percentage in MD direction/thermal contraction percentage in TD direction|?2.5 and average of thermal contraction percentage in MD direction and thermal contraction percentage in TD direction?3%.

Abstract: A semiconductor device is provided. The semiconductor device includes an active region, a gate line, a first metal interconnect, a power rail, and a second metal interconnect. The gate line overlaps the active region and extends along a first direction. The first metal interconnect overlaps the active region and the gate line. The first metal interconnect extends along a second direction intersecting the first direction. The power rail is disposed in a higher layer than the first metal interconnect. The power rail extends along the second direction. The second metal interconnect is disposed in a same layer as the power rail, the second metal interconnect extends along the second direction.

Abstract: The present invention provides a display panel, a fabricating method thereof and a display device. The display panel comprises a pixel region and a fan-out region, first signal lines and second signal lines are provided to intersect each other in the pixel region, and extend into the fan-out region, respectively, a first insulation layer is provided between the first signal lines and the second signal lines, a second insulation layer is provided on the second signal lines, the second insulation layer comprises at least four layers of structures, and a density of each layer of structure of the second insulation layer decreases gradually along a direction away from the first insulation layer. A size of the via hole formed in the second insulation layer by etching is smaller than that of the via hole formed in the prior art.

Abstract: Described herein are methods for flattening a substrate, such as a semiconductor wafer, to reduce bowing in such substrates. Methods include treating or bombarding a backside surface of a substrate with particles of varying doses, densities, and spatial locations. Particle bombardment and selection is such that the substrate becomes more planar by selectively increasing or decreasing z-height points to reduce overall deflection. One or more tensile or compressive films can be added to the backside surface to be selectively relaxed at specific point locations. Such methods can correct bowing in substrates resulting from various fabrication processes such as thermal annealing.