Abstract: There are provided a 3-D semiconductor device and a manufacturing method thereof. The 3-D semiconductor device includes a substrate extending along a first plane defined by first and second x and y directions, the substrate having a pipe transistor formed therein, a plurality of word lines spaced apart at regular intervals along a third direction z perpendicular to the first and second x and y directions; a first vertical plug connected to a first end of the pipe transistor by passing vertically through the word lines; a second vertical plug, connected to a second end of the pipe transistor by passing vertically through the word lines; a bit line connected to a top surface of the first vertical plug; and a source line connected to a top surface of the second vertical plug, wherein the first and second vertical plugs have different size.

Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

Abstract: A method of manufacturing a semiconductor device may include forming an insulating layers on a substrate, forming a plurality of holes in an upper portion of the insulating layer, forming a mask layer having openings exposing at least a first set of the plurality of holes, etching a lower portion of the insulating layer exposed by one of the plurality of holes which is exposed by the mask layer to form a through hole in the insulating layer in combination with the one of the plurality of holes, and forming a conductive structure in the through hole.

Abstract: Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a semiconductor chip, a mounting block on which a first mounting device is mounted on a substrate that includes a circuit formed thereon, and an interconnection part configured to electrically connect the semiconductor chip to the mounting block.

Abstract: A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.

Abstract: The present invention provides a MIS-type semiconductor device having a ZrOxNy gate insulating film in which threshold voltage shift is suppressed, thereby achieving stable operation. In the MIS-type semiconductor device having a gate insulating film on the semiconductor layer and a gate electrode on the gate insulating film, with a gate applied voltage of 5 V or more, the gate insulating film is formed of ZrOxNy (x and y satisfy the relation: x>0, y>0, 0.8?y/x?10, and 0.8?0.59x+y?1.0). The MIS-type semiconductor device having such a gate insulating film can perform stable operation because there is no shift in the threshold voltage even if a high voltage is applied to the gate electrode.

Abstract: A method of manufacturing a photoelectric conversion device includes forming a wiring structure above a semiconductor substrate including a photoelectric converter, forming, by a plasma CVD method, a first insulating film which contains hydrogen, above an uppermost wiring layer in the wiring structure, performing, after formation of the first insulating film, first annealing in a hydrogen containing atmosphere on a structure including the semiconductor substrate, the wiring structure, and the first insulating film, forming a second insulating film above the first insulating film after the first annealing, and performing, after formation of the second insulating film, second annealing in the hydrogen containing atmosphere on a structure including the semiconductor substrate, the wiring structure, the first insulating film, and the second insulating film.

Abstract: A method is described of radiatively cutting a wafer, the method comprising the steps of low power cutting of two trenches followed by high power cutting of a fissure. A single pulsed radiation beam is split into a first pulsed radiation beam for cutting at least one of the trenches and a second pulsed radiation beam for cutting the fissure. When cutting a fissure on the wafer in a cutting direction along a cutting street, the first and second radiation beams are directed simultaneously with the first radiation beam leading and the second radiation beam trailing. For cutting a fissure in the opposite cutting direction, a third pulsed radiation beam for trenching is split from said single pulsed radiation beam.

Abstract: A semiconductor structure includes a semiconductor substrate, at least a semiconductor layer formed on the semiconductor substrate, and at least a fin structure formed on the semiconductor layer. The semiconductor substrate includes a first semiconductor material, the semiconductor layer includes the first semiconductor material and a second semiconductor material, and the fin structure includes at least the first semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The semiconductor layer includes a first width, the fin structure includes a second width, and the second width is smaller than the first width.

Abstract: The production apparatus includes a shower head electrode, a susceptor for supporting a growth substrate, a first gas supply pipe, and a second gas supply pipe. The first gas supply pipe has at least one first gas exhaust outlet and supplies an organometallic gas containing Group III metal as a first gas, and the second gas supply pipe supplies a gas containing nitrogen gas as the second gas. The distance between the shower head electrode and the susceptor is greater than the distance between the first gas exhaust outlet of the first gas supply pipe and the susceptor.

Abstract: A method of manufacturing a semiconductor device, including forming an etching target film on a substrate; forming an anti-reflection film on the etching target film; forming a photoresist film on the anti-reflection film; exposing the photoresist film; performing heat treatment on the anti-reflection film and the photoresist film to form a covalent bond between the anti-reflection film and the photoresist film; and developing the photoresist film.

Abstract: Fabricating a semiconductor device can include forming a metal seed region over a substrate. The method can include forming a mask over a first portion of the metal seed region. The method can also include forming a metal region over the metal seed region and removing the mask. The method can include forming metal contact fingers on the semiconductor device, where the forming includes etching the first portion of the metal seed region with an etchant comprising an acid, an oxidizer and chloride ions.

Abstract: Aspects of the disclosure pertain to methods of forming conformal liners on patterned substrates having high height-to-width aspect ratio gaps. Layers formed according to embodiments outlined herein have been found to inhibit diffusion and electrical leakage across the conformal liners. The liners may comprise nitrogen and be described as nitride layers according to embodiments. The conformal liners may comprise silicon and nitrogen and may consist of silicon and nitrogen in embodiments. Methods described herein may comprise introducing a silicon-containing precursor and a nitrogen-containing precursor into a substrate processing region and concurrently applying a pulsed plasma power capacitively to the substrate processing region to form the conformal layer.

Abstract: A substrate having thereon a first dielectric layer, a second dielectric layer, and a hard mask layer is provided. A partial via is formed in the second dielectric layer and the hard mask layer. A first photoresist pattern with a first trench opening above the partial via and a second trench opening is formed on the hard mask layer. The hard mask layer and the second dielectric layer are etched through the first trench opening and the second trench opening, thereby forming a first dual damascene structure comprising a first trench and a first via, and a second trench in the second dielectric layer, respectively. A second photoresist pattern having a self-aligned via opening above the second trench is formed. The second dielectric layer is etched through the self-aligned via opening, thereby forming a second dual damascene structure comprising the second trench and a second via under the second trench.

Abstract: A method for manufacturing a structure implementing temporary bonding a substrate to be handled with a handle substrate, including: providing the substrate to be handled covered with a first metal layer, the first layer having a first grain size; providing the handle substrate covered with a second metal layer, the second layer having same composition as the first metal layer and a second grain size different from the first grain size; assembling the substrate to be handled and the handle substrate by thermocompression assisted direct bonding on the first and second metal layers; possibly treating the substrate to be handled assembled to the handle substrate; disassembling the assembly of the substrate to be handled and the handle substrate to form the structure, including an embrittlement thermal annealing of the assembly resulting in the handle substrate being detached.

Abstract: A method of forming an embedded polysilicon resistor body contact. According to the method, a transistor is formed in and above a crystalline active region that is positioned in a semiconductor layer of a multilayer semiconductor device. A resistor region is defined in single crystal semiconductor material of the semiconductor layer formed on a buried insulating layer. The resistor region is adjacent the transistor. An amorphized semiconductor material is formed in the resistor region. A barrier is formed in the amorphized semiconductor material. The barrier is between the transistor and an electrical body contact for the transistor. The amorphized semiconductor material is annealed, forming a polysilicon semiconductor. The barrier prevents the amorphized region from recrystallizing back to single crystal silicon.

Abstract: Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip including a plurality of first contact pads, the plurality of first contact pads facing the RDL; a second chip disposed between the first chip and the redistribution layer (RDL) wherein a portion of the first chip is disposed outside a lateral extent of the second chip; and a conductive via laterally separated from the second chip, the conductive via extending between the RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the second chip.

Abstract: One or more techniques or systems for mitigating peeling associated with a pad, such as a pad of a semiconductor, are provided herein. In some embodiments, a pad structure for mitigating peeling comprises a bond region located above a first region. In some embodiments, a first inter-layer dielectric region associated with the first region is formed in an inter-layer region under the pad. Additionally, a first inter-metal dielectric region associated with the first region is formed in an inter-metal region under the inter-layer region. In some embodiments, the first inter-metal region is formed under the first inter-layer region. In this manner, peeling associated with the pad structure is mitigated, at least because the first inter-metal dielectric region comprises dielectric material and the first inter-layer dielectric region comprises dielectric material, thus forming a dielectric-dielectric interface between the first inter-metal dielectric region and the inter-layer dielectric region.

Abstract: A semiconductor device of the present invention includes a first interlayer film having a first region and a second region, a MIM structure including a lower electrode formed on the second region, a first capacitance film formed on the lower electrode, and an upper electrode formed on the first capacitance film, a lower metal layer formed on the first region, and disposed in the same layer level with the lower electrode, an auxiliary metal layer disposed in the same layer level with the upper electrode, and opposed to the lower metal layer, a second interlayer film formed on the first interlayer film, and covering the auxiliary metal layer and the MIM structure, and a top metal layer formed on the second interlayer film, and penetrating through the second interlayer film to contact the auxiliary metal layer.

Abstract: There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.