Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Abstract: A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.

Abstract: A method includes performing a spin coating process. In the spin coating process, a first fluid is dispensed to a surface of a wafer. The method further includes performing an inspection of an edge area of the wafer. On the basis of the inspection of the edge area of the wafer, a defect analysis is performed. In the defect analysis, it is determined if the edge area of the wafer has a defect that is indicative of an insufficient coating of the surface of the wafer by the first fluid.

Abstract: Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. In some embodiments, systems for forming a solar cell on a substrate are provided, the systems comprising: a master shadow mask positioned adjacent to the substrate on a first side of the master shadow mask; a first blocking mask placed adjacent to a second side of the master shadow mask; and a deposition machine that deposits material on the substrate through holes in the master shadow mask and the first blocking mask.

Abstract: Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first integrated circuit package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect. The second package also includes a redistribution portion coupled to the first die and the package interconnect, an encapsulation layer at least partially encapsulating the first die and the package interconnect. The first pad may include a surface that has low roughness. The encapsulation layer may encapsulate the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect.

Abstract: A method to make a semiconductor device, a first SiO2 layer and a first Si3N4 layer are sequentially formed on the semiconductor substrate. The first SiO2 layer and the first Si3N4 layer are then patterned as etching mask to form a trench in a semiconductor substrate by a trench etching process. After this, a second SiO2 layer and a second Si3N4 layer are formed conformal onto the substrate. Anisotropic etching is then performed to remove the second Si3N4 and second SiO2 layer except on the trench sidewall. Then a thermal oxidation process is done to grow oxide only in trench bottom and at trench top corner. The radius of curvature of trench bottom and trench top corner is increased at the same time by this thermal oxidation process.

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Abstract: The present disclosure relates to a display substrate, a display device and a method for manufacturing the display substrate. The display substrate comprises a substrate, and a plurality of gate lines, a plurality of data lines and a plurality of common electrode lines which are formed above the substrate. The plurality of gate lines and the plurality of data lines are crossed to form a plurality of pixel units. Each of the plurality of pixel units comprises a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The display substrate further comprises connection electrodes located above the substrate. Each of the connection electrodes connects two adjacent common electrode lines.

Abstract: A method of manufacturing a capacitor for a semiconductor device includes forming a lower electrode, forming a dielectric layer on the lower electrode, forming a first upper electrode on the dielectric layer, adsorbing an organic silicon source onto a surface of the first upper electrode, and forming a second upper electrode on the first upper electrode onto which the organic silicon source is adsorbed. Related devices and fabrication methods are also discussed.

Abstract: A method of manufacturing an organic light-emitting display apparatus includes forming a pixel electrode, a bus electrode and a pixel defining layer on a same layer on a substrate, the pixel defining layer exposing a center of the pixel electrode and a portion of the bus electrode, forming an intermediate layer on the pixel-defining layer and on the pixel electrode and the bus electrode, orienting the substrate such that the intermediate layer is located underneath the substrate, forming an opening in the intermediate layer by irradiating the intermediate layer with a laser beam from underneath the intermediate layer to remove the intermediate layer on the bus electrode, exposing at least a portion of the bus electrode, and forming an opposite electrode such that the opposite electrode contacts the bus electrode via the opening in the intermediate layer.

Abstract: The present invention provides a vapor deposition apparatus capable of preventing abnormal film formation due to scattering in vapor deposition streams; and a method for producing an organic electroluminescent element which includes forming a patterned thin film with the vapor deposition apparatus. The present invention relates to a vapor deposition apparatus that includes a vapor deposition source equipped with a nozzle that ejects vapor deposition particles; an integrated limiting plate equipped with a first limiting plate including an opening that is in front of the nozzle, and with second limiting plates placed in the opening in the first limiting plate; and a mask including slits. The present invention also relates to a method for producing electroluminescent elements that includes a vapor deposition step of forming a patterned thin film with the vapor deposition apparatus.

Abstract: A manufacturing method for a semi-floating gate device, mainly comprising a manufacturing method for a floating gate and a floating gate opening area, and the specific process thereof is: reserving a hard mask layer after a U-shaped groove is formed, growing a gate dielectric layer on a surface of the formed U-shaped groove, depositing and etching back a first layer of polysilicon to protect the gate dielectric layer, etching away the exposed gate dielectric layer and hard mask layer, then covering a formed structure to deposit a second layer of polysilicon, then etching a formed polysilicon layer by a photoetching process and an etching process so as to form a floating gate, and forming a floating gate opening area in a self-aligning way. The manufacturing method can simplify the existing manufacturing process for a semi-floating gate device, reduce the difficulty in manufacturing the semi-floating gate device with a U-shaped channel, and improve the yield of the semi-floating-gate device.

Abstract: A method of forming a superjunction device includes providing a semiconductor layer having first and second opposing main surfaces and a first doping concentration of a dopant of a first conductivity type, forming at least one device proximate the first main surface, forming at least one trench adjacent to the device and extending into the semiconductor layer from the first main surface, doping at least a portion of a sidewall of the trench with a dopant of a second, different conductivity type to form a first region in the semiconductor layer adjacent to the sidewall and extending at least partially between the first and second main surfaces, providing a substrate with a first dielectric layer arranged thereon, bonding the first dielectric layer to the first main surface to cover the trench and at least a portion of the device, and removing the substrate.

Abstract: The invention relates to a field of semiconductor manufacturing technology, more particularly, to a method for preparing three-dimensional integrated inductor-capacitor structure, which can realize the inductor-capacitor of three-dimensional structure, and form three-dimensional spiral inductor centering on the magnetic cores of single direction around through the preparation of the interconnected top metal conducting wires and bottom metal conducting wires, which can gain capacitance and inductance at the same time in a relatively small space, and reduce the production costs, and also greatly improves the inductance magnetic flux in order to increase the inductance value and reduce eddy current, and improve the quality factor Q value and the performance of inductance coil.

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes both a static wire mesh and an active wire mesh. The wire meshes can be formed in the same layer over the circuits to be protected or in different layers. The wire meshes also may cover the entire chip area or only predetermined areas, such as over secure memory and register areas. The wire meshes are connected to a tamper detection module, which monitors the meshes and any signals transmitted via the meshes to detect attempts to access the protected circuits via micro-probing.

Abstract: Disclosed is a thin film transistor (TFT) of a display apparatus which reduces a leakage current caused by a hump and decreases screen defects. The TFT includes an active layer and a first gate electrode with a gate insulator therebetween, and a source electrode and a drain electrode respectively disposed at both ends of the active layer. The gate electrode branches as a plurality of lines and overlaps the active layer. The active layer includes one or more channel areas between the source electrode and the drain electrode, one or more dummy areas, and a plurality of link areas between the one or more channel areas to connect the one or more channel areas in one pattern. A length of each of the one or more dummy areas extends from an edge of a corresponding channel area.

Abstract: A wafer processing method includes a cut groove forming step of positioning, from a back side of the substrate, a cutting blade to an area corresponding to a division line to form cut grooves in such a manner that the cutting blade does not reach a functional layer and part of a substrate is left, and a functional layer cutting step of performing irradiation with a laser beam along the division lines formed in the functional layer forming a wafer to perform ablation processing for the functional layer and cut the functional layer. In the cut groove forming step, the cut grooves are formed along the division lines in such a manner that an uncut part is left in a peripheral area of the wafer.

Abstract: When a thin film is formed by an application method, damage to a substrate or existing electrodes and functional layers can be reduce. A method for manufacturing an electronic device comprising two or more electrodes, and an organic thin film provided between the two or more electrodes, the method comprising the steps of: forming a coating film by applying a coating liquid that comprises a material having a crosslinking group, and forming the organic thin film by repeating an irradiation of electromagnetic waves to the coating film to cross-link with the crosslinking group.

Abstract: One embodiment of the present invention sets forth a technique for packaging an integrated circuit die. The technique includes bonding a first surface of the integrated circuit die to a first substrate via a first plurality of solder bump structures and bonding a second substrate to a second surface of the integrated circuit die. The technique further includes bonding the first substrate to a third substrate via a second plurality of solder bump structures and, after bonding the first substrate to the third substrate, removing the second substrate from the second surface of the integrated circuit die. The technique further includes disposing a heat sink on the second surface of the integrated circuit die.