Abstract: Provided are an organic-inorganic-hybrid perovskite nanocrystal particle light-emitter having a two-dimensional structure, a method for producing the same, and a light emitting device using the same. The organic-inorganic-hybrid perovskite nanocrystal particle light-emitter having a two-dimensional structure comprises an organic-inorganic-hybrid perovskite nanocrystal structure having a two-dimensional structure which can be dispersed in an organic solvent. Accordingly, the nanocrystal particle light-emitter comprises an organic-inorganic-hybrid perovskite nanocrystal having a crystal structure combining FCC and BCC; forms a lamellar structure where organic planes and inorganic planes are accumulated in an alternating manner; and can exhibit high color purity by confining excitons in the inorganic planes.

Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconducting layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate.

Abstract: A method of manufacturing joined body including: firstly, putting sheet material in intimate contact with first substrate to cover, with resin layer of sheet material, areas of first substrate including first area, boundary area surrounding first area, and second area located across from first area with respect to boundary area, sheet material being laminate including resin layer and separable layer, resin layer containing uncured sealing resin; secondly, curing sealing resin in part of resin layer covering boundary area; thirdly, removing, along with separable layer, part of resin layer covering second area in one direction from one end towards the other of two ends of second area; and fourthly, joining first substrate and second substrate together by arranging second substrate to face first substrate and curing sealing resin with parts of resin layer covering boundary area and first area located between second substrate and first substrate.

Abstract: A light source module according to an embodiment includes: a flexible printed circuit board that has first and second pads; and a plurality of light emitting chips that are arranged on the first pads of the flexible printed circuit board, respectively, wherein the plurality of light emitting chips include a plurality of first arrays that are arranged in a first direction and second arrays that are arranged in a second direction that is different from the first direction, at least two of light emitting chips in each first array are connected to each other by the flexible printed circuit board, light emitting chips in each second array are electrically isolated from each other, the light source module further includes connection members, each of which is connected to at least one of the light emitting chips of the second array and a corresponding second pad of the flexible printed circuit board, and the connection members extend in the second direction.

Abstract: The purpose of the invention is to eliminate an abnormal current at an edge of a semiconductor layer in a thin film transistor. The invention is: A thin film transistor having a semiconductor layer comprising: a channel, a drain and a source are formed in the semiconductor layer, the channel has a channel length and a channel width, a LDD (Light Doped Drain) is formed between the channel and the drain or between the channel and the source, the LDD including a first LDD area, which is formed at a center of the LDD in the direction of the channel width, and a second LDD area, which is formed at an edge of the LDD in the direction of the channel width, wherein a width of the second LDD area in the channel length direction is bigger than a width of the first LDD area in the channel length direction.

Abstract: Improvements are achieved in the characteristics of a nonvolatile memory. In plan view, in a first isolation region which is an element isolation region surrounded by a first fin, a second fin, a memory gate electrode, and another memory gate electrode, a protruding portion is provided. In a second isolation region which is the element isolation region overlapping the memory gate electrode in plan view, a second isolation portion is provided to set the protruding portion higher in level than the second isolation portion. In a step of lowering a top surface of the element isolation region located between the first and second fins, a part of the element isolation region located between the first and second fins is covered with a mask film to form the protruding portion. Using the protruding portion, a short circuit between the memory gate electrodes due to a gate residue is prevented.

Abstract: Embodiments of the invention include a semiconductor light emitting device, a first wavelength converting member disposed on a top surface of the semiconductor light emitting device, and a second wavelength converting member disposed on a side surface of the semiconductor light emitting device. The first and second wavelength converting members include different wavelength converting materials.

Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

Abstract: Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect structures, as well as methods for integrating MIM capacitor formation as part of an air gap process flow for fabricating on-chip interconnect structures. For example, a semiconductor device includes a dielectric layer with a first pattern of metal lines and second pattern of metal lines. Air gaps are disposed in spaces between the metal lines. Portions of the spaces between the metal lines of the first pattern of metal lines include a conformal layer of insulating material disposed on sidewalls of the metal lines and metallic material that fills the spaces between the metal lines. The first pattern of metal lines comprises a first capacitor electrode, the metallic fill material comprises a second capacitor electrode, and the conformal layer of insulating material comprises an insulating layer of a MIM capacitor structure.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: A fluoride phosphor including a sheet-like crystal and a manufacturing method and an application therefore are disclosed. The fluoride phosphor has a chemical formula A2[MF6]:Mn4+, with Mn4+ as an activator. The A is Li, Na, K, Rb, Cs, NH4 or a combination thereof. The M is Ge, Si, Sn, Ti, Zr or a combination thereof. The sheet-like crystal has a thickness d. A crystal flat surface of the sheet-like crystal has a maximum length a. The maximum length a is defined as a distance between two end points on an edge of the crystal flat surface and farthest from each other. 8?a/d?35.

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.

Abstract: The invention provides an OLED display panel and the production process thereof, which relates to the technical field of display, may improve the surface flatness and the water-oxygen permeation resistance of the flexible base substrate, improve the light output ratio of the display panel, and may control the center wavelength of the electroluminescence spectrum.

Abstract: A method for preparing a quantum dot mixture with a bimodal size distribution includes steps of: a) preparing a mixed cationic precursor solution, b) preparing a first anionic precursor solution and a second anionic precursor solution, c) conducting a nucleation reaction at a nucleation temperature for a predetermined nucleation time, and d) conducting a crystallite growth reaction at a crystallite growth temperature for a predetermined crystallite growth time.

Abstract: Embodiments of the invention include a semiconductor light emitting diode attached to a substrate. A first region of wavelength converting material is disposed on the substrate. The wavelength converting material is configured to absorb light emitted by the semiconductor light emitting diode and emit light at a different wavelength. In the first region, the wavelength converting material coats an entire surface of the substrate. The substrate is disposed proximate a bottom surface of an optical cavity. A second region of wavelength converting material is disposed proximate a top surface of the optical cavity.

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

Abstract: A method for fabricating an organic electro-luminescence device, comprising: forming a first conductive layer comprising a first electrode and a contact pattern on a substrate; forming a first mask on the first conductive layer, the first mask comprising an opening for exposing a portion of the first electrode and a portion of the contact pattern; forming a patterned organic functional layer by shielding of a second mask, the patterned organic functional layer covering the first mask and the first electrode exposed by the first mask, and the second mask being disposed over the first mask to shield the portion of the contact pattern exposed by the opening; forming a second conductive layer and patterning the second conductive layer by removing the first mask and a portion of the second conductive layer on the first mask to form a second electrode electrically connected to the contact pattern.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.