Abstract: A light-emitting device in accordance with the present invention includes a mounting substrate; an LED chip bonded to a surface of the mounting substrate with a bond; and an encapsulating portion covering the LED chip. The bond transmits light from the LED chip. The mounting substrate includes: a light-transmissive member having a planar size larger than that of the LED chip; and first and second penetrating wirings which penetrate the light-transmissive member in the thickness direction thereof and are electrically connected to first and second electrodes of the LED chip via first and second wires, respectively. The light-transmissive member includes at least two light-transmissive layers with different optical properties which are stacked in the thickness direction. A light-transmissive layer of the light-transmissive layers which is farther from the LED chip is higher in reflectance to the light.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

Abstract: Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure.

Abstract: The present invention relates to an epitaxial wafer for a light-emitting diode wherein the peak emission wavelength is 655 nm or more, and it is possible to improve reliability. The epitaxial wafer for light-emitting diodes includes a GaAs substrate (1) and a pn-junction type light-emitting unit (2) provided on the GaAs substrate (1), wherein light-emitting unit (2) is formed as a multilayer structure in which a strained light-emitting layer and a barrier layer are alternately stacked, and the composition formula of the barrier layer is (AlXGa1-X)YIn1-YP (0.3?X?0.7, 0.51?Y?0.54).

Abstract: A light-emitting diode chip includes a semiconductor body including a radiation-generating active region, at least two contact locations electrically contacting the active region, a carrier and a connecting medium arranged between the carrier and the semiconductor body, wherein the semiconductor body includes roughening on outer surfaces facing the carrier, the semiconductor body mechanically connects to the carrier by the connecting medium, the connecting medium locally directly contacts the semiconductor body and the carrier, and the at least two contact locations are arranged on the upper side of the semiconductor body facing away from the carrier.

Abstract: Disclosed are a light emitting device, a light emitting device package and a light emitting module. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first and second conductive semiconductor layers; a support member under the light emitting structure; a reflective electrode layer between the second conductive semiconductor layer and the support member; and first to third connection electrodes spaced apart from each other in the support member. The second connection electrode is disposed between the first and third connection electrodes, the first and third connection electrodes are electrically connected with each other, and the support member is disposed at a peripheral portion of the first to third connection electrodes.

Abstract: An LED manufacturing method includes steps of: providing a substrate including a first surface; forming a first portion of a first semiconductor layer on the first surface in a first atmosphere including a first carrier gas; and forming a second portion of the first semiconductor layer on the first portion in a second atmosphere including a second carrier gas; wherein a plurality of first cavities is formed on a surface of the first portion during forming the first portion; and wherein the plurality of first cavities is transformed to a plurality of second cavities during forming the second portion, and one of the second cavities includes a first inclined surface and a second inclined surface above the first inclined surface.

Abstract: The parasitic capacitance formed by a gate electrode, a contact, and a side wall is reduced. The gate electrode and the side wall are covered by an insulating layer. The contact passes through the insulating layer and is connected to a diffusion layer. Then, an air gap is located between the side wall and the contact. The air gap faces the contact at the side face on the contact side via the insulating layer.

Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

Abstract: A method of manufacturing a semiconductor device, by etching a region of an SOI substrate so that only a portion of the original semiconductor is present above the insulator layer. After etching has occurred, a different semiconductor material is grown in the etched region, and fins are formed. An isolation layer is deposited to a height above that the base semiconductor of the etched region.

Abstract: A method of manufacturing an alignment film is provided, and has steps of determining printing regions for an alignment agent, which including display portions and transfer portions; printing the alignment agent within the printing regions to form an alignment thin layer; and performing an alignment process to the alignment thin layer to form the alignment film. The unevenness on the edge of the alignment film is moved away from the display portions by expanding the printing regions for the alignment agent, so as to promote the imaging quality of the finished LCD.

Abstract: Embodiments of forming an image sensor with an organic photodiode are provided. The organic photodiode uses dual electron-blocking layers formed next to the anode of the organic photodiode to reduce dark current. By using dual electron-blocking layers, the values of highest occupied molecular orbital (HOMO) for the neighboring anode layer and the organic electron-blocking layer are matched by one of the dual electron-blocking layers to form a photodiode with good performance. The values of the lowest occupied molecular orbital (LOMOs) of the dual electron-blocking layers are selected to be lower than the neighboring anode layer to reduce dark current.

Abstract: An embodiment of a process for manufacturing a system for electrical testing of a through via extending in a vertical direction through a substrate of semiconductor material envisages integrating an electrical testing circuit in the body to enable detection of at least one electrical parameter of the through via through a microelectronic buried structure defining an electrical path between electrical-connection elements towards the outside and a buried end of the through via; the integration step envisages providing a trench and forming a doped buried region at the bottom of the trench, having a doping opposite to that of the substrate so as to form a semiconductor junction, defining the electrical path when it is forward biased; in particular, the semiconductor junction has a junction area smaller than the area of a surface of the conductive region in a horizontal plane transverse to the vertical direction, in such a way as to have a reduced reverse saturation current.

Abstract: An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion.

Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.

Abstract: According to one embodiment, a semiconductor analysis microchip configured to detect a fine particle in a sample liquid, including a semiconductor substrate, a first flow channel provided in the semiconductor substrate, to which the sample liquid is introduced, and a pore provided in the first flow channel and configured to pass the fine particle in the sample liquid.

Abstract: An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.

Abstract: The present invention relates to a display device, and a manufacturing method thereof. The display device includes a first insulation substrate; gate lines and data lines positioned on the first insulating substrate. The gate lines and data lines are insulated from each other and crossed each other. A first passivation layer positioned on the gate lines and the data lines, and including a first contact opening. A color filter positioned on the first passivation layer, and including an opening. An organic insulation layer positioned on the color filter, and including a contact hole, in which the first contact opening is larger than the opening. The organic insulation layer covers the color filter and the contact opening.

Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.