Abstract: A semiconductor device includes a mounting substrate with a land having a first surface and a second surface higher than the first surface, a side-emission type light emitting device including an external connecting terminal disposed on the first surface, and a bonding member disposed at least on the second surface to bond the external connecting terminal and the land.

Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.

Abstract: A microelectromechanical system (MEMS) sensor device includes a package housing having a top member, bottom member, and a spacer coupled the top member to the bottom member, defining a cavity. At least one sensor circuit and a MEMS sensor disposed within the cavity of the package housing. A first opening formed on the package housing a control device embedded within the package housing is electrically coupled to the sensor circuit and is controlled to tune the MEMS sensor from a directional mode to an omni-directional mode.

Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Abstract: Embodiments of forming an image sensor with an organic photodiode are provided. The organic photodiode uses dual electron-blocking layers formed next to the anode of the organic photodiode to reduce dark current. By using dual electron-blocking layers, the values of highest occupied molecular orbital (HOMO) for the neighboring anode layer and the organic electron-blocking layer are matched by one of the dual electron-blocking layers to form a photodiode with good performance. The values of the lowest occupied molecular orbital (LOMOs) of the dual electron-blocking layers are selected to be lower than the neighboring anode layer to reduce dark current.

Abstract: Described is a 6T SRAM cell which comprises: a first n-type transistor with a gate terminal coupled to word-line, source/drain terminal coupled to a first bit-line and drain/source terminal coupled to a first node; and a second n-type transistor with a source terminal coupled to a first supply node, a drain terminal coupled to the first node, and a gate terminal for coupling to multiple terminals, wherein the gate terminal includes a capacitor to increase coupling capacitance of the second n-type transistor. Described is a method which comprises: forming a metal gate in a first direction; forming a first spacer in the first direction on one side of the metal gate, the first spacer having a first dimension; and forming a second spacer in the first direction on another side of the metal gate, the second spacer having a second dimension which is substantially different from the first dimension.

Abstract: An organic light-emitting diode (OLED) display apparatus including a substrate, an insulation layer on the substrate, and an align mark formed of an insulation material, wherein an upper surface of the insulation layer contacts a lower surface of the align mark.

Abstract: One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In some embodiments, the NMOS transistor includes a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region, the gate stack is between the first PP region and the second NP region, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region enables ESD current to discharge based on a low trigger voltage for the NMOS transistor.

Abstract: A corrosion-resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. An array of intersecting metal lines forming windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent entry of moisture.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.

Abstract: Provided are semiconductor devices. A semiconductor device includes a first well formed in a substrate; an element isolation layer formed on the first well; a second well formed in the first well on a first side of the element isolation layer; a third well formed in the second well, the third well has a higher concentration of impurities than the second well; a first electrode electrically connected to the third well; a fourth well formed in the first well on a second side of the element isolation layer; a fifth well formed in the fourth well, the fifth well has a different conductivity type from the fourth well; a second electrode electrically connected to the fifth well; and a sixth well overlapping the fourth well, the sixth well has a lower concentration of impurities than the fourth well.

Abstract: An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.

Abstract: A display apparatus and a method of manufacturing the same are disclosed. The display apparatus includes: a first substrate including a light emitting diode part including a plurality of light emitting diodes regularly arranged on the first substrate; and a second substrate including a TFT panel unit including a plurality of TFTs driving the light emitting diodes. The first substrate and the second substrate are coupled to each other so as to face each other such that the light emitting diodes are electrically connected to the TFTs, respectively. The display apparatus is implemented using micro-light emitting diodes formed of nitride semiconductors and thus can provide high efficiency and high resolution to be applicable to a wearable apparatus while reducing power consumption.

Abstract: A method for fabricating an organic electro-luminescence device, including: on a substrate, forming a first conductive layer including a first electrode and a first contact pattern electrically insulated therefrom; on the first conductive layer, forming a first mask including a release film, a base film disposed between the release film and the first conductive layer and an opening for partially exposing the first electrode and the first contact pattern; by shielding of a second mask, forming a patterned organic functional layer partially covering the first mask and the first electrode exposed by the first mask; removing the second mask; forming a second conductive layer over the structure aforesaid; and patterning the second conductive layer by removing the release film and the second conductive layer formed thereon to form a second electrode electrically connected to the first contact pattern and a second contact pattern electrically connected to the first electrode.

Abstract: A method for fabricating an organic electro-luminescence device, comprising: forming a first conductive layer comprising a first electrode and a contact pattern on a substrate; foil ling a first mask on the first conductive layer, the first mask comprising an opening for exposing a portion of the first electrode and a portion of the contact pattern; forming a patterned organic functional layer by shielding of a second mask, the patterned organic functional layer covering the first mask and the first electrode exposed by the first mask, and the second mask being disposed over the first mask to shield the portion of the contact pattern exposed by the opening; forming a second conductive layer and patterning the second conductive layer by removing the first mask and a portion of the second conductive layer on the first mask to form a second electrode electrically connected to the contact pattern.

Abstract: A sealing structure with high air-tightness and an organic electroluminescence device with high air-tightness are provided regardless of a pattern of a first metal layer overlapping with glass frit. A second metal layer is provided in a region where a common power supply line overlaps with the glass frit. Since laser light is absorbed or reflected by the second metal layer, the glass frit can be uniformly heated. Therefore, an object to be sealed can be sealed with a low-melting-point glass in which a crack is not easily generated.

Abstract: A packaged semiconductor device includes a semiconductor component, first and second heat dissipation means disposed between the semiconductor component and the first and second main faces, respectively, encapsulated by an encapsulant, the shape of the packaged semiconductor device being non-rectangular cuboid.

Abstract: Provided are a solid-state imaging element, which suppresses occurrence of a dark current and a white spot and even suppresses occurrence of a residual image, and a manufacturing method for the solid-state imaging element. A solid-state imaging element (1) is provided with: a gate electrode (4) above a substrate (2); a charge storage region (5) formed at a position inside the substrate (2) and apart from a top surface (2a) of the substrate (2); a read region (6) formed at a position inside the substrate (2) and on the opposite side to the charge storage region (5) with the gate electrode (4) interposed therebetween; a channel region (7, 8) formed inside the substrate (2) and immediately below the gate electrode (4); and a shield region (9) and an intermediate region (10) formed inside the substrate (2) and between the top surface (2a) of the substrate (2) and the charge storage region (5).

Abstract: The present disclosure provides a method of preparing a chalcogen containing solution that is hydrazine free and hydrazinium free, wherein the method comprises: providing a predetermined amount of elemental chalcogen; providing a predetermined amount of elemental sulfur; providing an amine solvent; and combining the predetermined amount of elemental chalcogen and the predetermined amount of elemental sulfur in the amine solvent, thereby dissolving the elemental chalcogen and the elemental sulfur in the amine solvent. The chalcogen containing solution can advantageously be used as a precursor for the formation of a chalcogen containing layer on a substrate.