Abstract: A cloning technique enables efficient and substantially instantaneous creation of a clone that is a writable copy of a “parent” virtual volume (vvol) in an aggregate of a storage system. A base snapshot is provided from the parent vvol. In addition, a new vvol is created, along with a new file system identifier, a new subdirectory in the aggregate and a new storage label file. The new vvol is embodied as a clone and comprises an appropriately sized container file, wherein initially the container file has no data. Moreover, a volume information (volinfo) block for the clone is created that is a slightly modified version of the volinfo block from the base snapshot; the modified volinfo block is written to the container file. The clone is then instantiated by loading a file system associated with the new vvol onto the clone and bringing the clone “online”.

Abstract: A memory system comprising router nodes. A plurality of router nodes are configured to route data between a memory controller and memory modules. The topology of the system comprises a hierarchy of one or more levels. Each of the levels includes one or more router nodes which may be configured to forward received data to another router node at the same level, or forward received data to a next lower level in the hierarchy. Router nodes in the system are configured to correspond to a particular level and position within the hierarchy. The memory controller generates a broadcast transaction to router nodes in the system. In response to receiving the transaction, the router nodes configure their internal routing mechanisms. Subsequently, the controller generates a memory access which is then routed by the router nodes to the target memory modules. Routing is such that memory modules not targeted by the memory access do not see the memory access.

Abstract: In the present invention, archive volumes are created in accordance with the size of data that is to be archived, and hence the storage regions are used in an efficient manner. The archive server acquires the data to be archived, via the application server, and detects the size of that data. The archive server issues an instruction to the storage device to cause the the storage device to generate an archive volume having a volume size corresponding to the data size of the data to be archived. The archive server writes the data to be archived to the volume having a storage capacity of the required size, and an access restriction and retention term are respectively established for the volume.

Abstract: A clone splitting technique enables efficient online splitting of blocks shared between a parent virtual volume (vvol) and a clone in accordance with a shared block splitting procedure executing on a storage system. Online splitting of shared blocks denotes allowing execution of read/write operations directed to the clone, as well as to the parent vvol, as the shared blocks are split. The clone splitting technique removes any connection between a clone and its parent vvol, thereby allowing the clone to be used as a first-class volume. Moreover, the technique removes such connection while allowing both the clone and parent vvol to remain available online and writeable (accessible) to clients during the shared block splitting procedure.

Abstract: A system and method creates a writable clone of a read-only volume. A base snapshot is generated on a source volume on a source storage system and is duplicated as a read-only base snapshot replica on a target volume on a destination storage system. A copy (“clone) is then substantially instantaneously created from the read-only base snap-shot replica, thereby creating a writable clone of a read-only volume.

Abstract: A low overhead method for identifying memory leaks is provided. The low overhead method includes a) detecting completion of a garbage collection cycle; and b) identifying a boundary between used objects in memory and free memory space. The steps of a) and b) are repeated and then it is determined if there is an existing memory leak based upon evaluation of boundary identifiers. A computer readable media and a system for identifying memory leaks for an object-oriented application are also provided.

Abstract: A method for identifying memory leak causes is provided. The method initiates with tracking a number of allocations of objects during a time period. Potentially leaking objects are identified and object lifetime tracking instrumentation is injected into the code to track potentially leaking objects. Then, object lifetime logs are generated for each of the potentially leaking objects. A computer readable medium and a system are also provided.

Abstract: Embodiments of the present invention provide a data storage apparatus with new features to more easily enable atomic transactions. Rather than having the host system issue the multiple logging commands to the data storage apparatus, the data storage apparatus can be modified so that it can perform the logging function itself. In one embodiment, a data storage controller of a data storage apparatus for implementing an atomic transaction comprises a receiving module configured to receive from a host one or more commands to be executed as an atomic transaction; a log recording module, configured to record in a nonvolatile storage a log containing the one or more commands of the atomic transaction, the log to be administered by the data storage controller and not by the host; and an execution module configured to perform the one or more commands of the atomic transaction.

Abstract: A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Next, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.

Abstract: An internal nonvolatile memory contains a program to be executed during a rewrite operation mode. During the rewrite operation mode a CPU core writes received rewrite data to an external nonvolatile memory according to a program in the internal nonvolatile memory. A first selector circuit transmits a first chip select signal to the external nonvolatile memory when a mode signal indicates a normal operation mode, and transmits the first chip select signal to the internal nonvolatile memory when the mode signal indicates the rewrite operation mode. Since the activation of the internal nonvolatile memory is inhibited during the normal operation mode, it is possible to prevent erroneous execution of the program in the internal nonvolatile memory during the normal operation mode, and to prevent data rewrite to the external nonvolatile memory.

Abstract: A device for writing data in a processor to memory at unaligned location. The data is stored in an internal register of the processor for writing to unaligned addresses of a memory partitioned by word boundaries into a plurality of words. A rotator is coupled to the internal register for rotating data of the internal register to a first position in accordance with written unaligned address. A store combine register is coupled to the rotator for temporarily storing data of the rotator. A mask selector is coupled to the rotator and the store combine register for selectively masking their data in accordance with the written unaligned address and storing the data masked to the memory.

Abstract: A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Then, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.

Abstract: A processor device capable of cross-boundary alignment of plural register data and the method thereof. The processor includes a decoder to decode a multiple shift instruction, a register unit with plural N-bit registers, a shifter to combine a first and a second output contents of the register unit to form a 2N-bit word and shift the word by w bits, thereby outputting first N bits of the word shifted, a controller to set the register unit in accordance with the multiple shift instruction decoded, thereby reading contents of corresponding registers for shifting w bits by the shifter and then writing an output of the shifter to the register unit.

Abstract: A method and apparatus for aggregating storage devices is disclosed. A package for providing high density storage uses a carrier housing for holding multiple storage devices proximate to one another and aligned in a row, and an access device, coupled to the carrier housing, aggregates the physical addresses of the storage devices into logical addresses and making the logical addresses available over a connection.

Abstract: A method and apparatus for providing high-density storage is disclosed. A plurality of storage devices is aggregated in a package. A package-level controller is coupled to a carrier housing holding a plurality of storage devices, wherein the package-level controller provides a RAID logical configuration at a package-level for the storage devices held in the carrier housing. A controller may also be provided for virtualizing the logical addresses as at least one aggregate volume to provide a layer of abstraction to the storage devices. The package may be inserted into a storage system designed to manage multiple packages.

Abstract: The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer.

Abstract: The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.

Abstract: A computer system and method for efficient storage and retrieval of data. The inventive computer system may comprise means for storing data, wherein data are allocated to predetermined categories that are components of at least one stored categorical structure forming an object model, wherein attributes that are inherited within the categorical structure are allocated to the categories; at least one inquiry unit for making queries relating to the stored data; and at least one inference unit used to evaluate declarative rules linking at least one of said categories and said attributes.

Abstract: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.

Abstract: A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in response to N?1 number of the align control signals for receiving N-bit data and outputting the N-bit data in a parallel fashion; and a outputting block in response to the remaining align control signal for receiving the N-bit data in the parallel fashion and synchronizing the N-bit data with the remaining align control signal having a N/2 external clock period to thereby generating the synchronized N-bit data as a prefetched data.