Abstract: Techniques to assure genuineness of data stored on a storage device are provided. The storage device includes a storage controller that conducts I/O operations and management operations. A description of management operations and corresponding timestamps are recorded to an operation log stored in a memory. The memory additionally stores an attribute for each storage volume of the storage device. Write access to each of the storage volumes is dependent on the attribute.

Abstract: A memory controller, such as a SDRAM controller, forms a queue of memory access requests to maximize efficient use of the bandwidth of the memory data bus. More specifically, the SDRAM controller pre-calculates the number of data bursts required to retrieve all the required data from the SDRAM, and the starting address for each of the data bursts, and queues the access requests for these data bursts such that the data bursts may be retrieved without incurring the usual read latency for each data burst.

Abstract: A method for adaptation of data organization by a data storage system controller is disclosed. Data organization in a data storage system is adapted according to varying workload profiles and system constraints. The data storage system also consists of a plurality of data storage units. On receipt of a request to write data, various workload and data storage system parameters are determined. On the basis of these parameters, target data storage units and appropriate data organization schemes are optimally selected. In the case where the volume of data to be written is less than a threshold value, a RAID organization scheme is preferred. In this scheme the data is written to the selected drives simultaneously. In the case where the volume of data to be written is more than the threshold value, a power managed RAID organization scheme, where all data drives need not be simultaneously powered on, is used.

Abstract: Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory arrangements connected to the buffer chip are provided. A buffer circuit may receive first initialization data specifying a first set of available memory arrangement addresses and associate one or more of the first set of available memory arrangement addresses with the one or more memory arrangements connected to the buffer chip. The buffer circuit may also generate second initialization data specifying the set of available memory arrangement addresses available after the association. The second initialization data may be transmitted to another buffer circuit for use in address allocation or back to a memory access control unit.

Abstract: A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

Abstract: Disclosed are a system, a method, and an article of manufacture to provide for configuring an automated data storage library having one or more storage frames that operate with different types of data storage media. The automated data storage library is configured to operate with sequential storage shelf addresses assigned to consecutive storage frames that use the same type of data storage media. The storage frames that operate with different types of data storage media may be physically assembled in any order. The automated data storage library may be expanded by attaching storage frames that operate with different types of data storage media in any order while maintaining sequential storage shelf addresses that span across multiple library frames.

Abstract: An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such as a number of data processing units in use. In some embodiments, apparatus and systems, as well as methods and articles, may operate to select a memory access group size of about 2N memory banks responsive to receiving an indication of a change in a protocol type, wherein the group is selected from a number B of banks, and N is associated with the protocol type.

Abstract: A method of determining a configuration of a collection of storage units, includes: generating a configuration, identifying for a specific configuration by use of a configuration identifier; and assigning the specific configuration to the first labels of all storage units and then to the second labels of all storage units, and utilizing the configuration identifier to determine the most recent configuration successfully written to all disks in the configuration.

Abstract: Content addressable data storage and compression for semi-persistent computer memory including providing a chunk of data that is a quantity of input data; retrieving a memory block from semi-persistent computer memory; searching for a segment of the chunk that matches the memory block; and if a matching segment is found: discarding the matching segment; providing a retrieval key for the memory block as a retrieval key for the matching segment; identifying an unmatched portion of the chunk that does not match the memory block; identifying a free memory block of a file system; storing the unmatched portion semi-persistently in the free memory block; and providing a retrieval key for the unmatched portion.

Abstract: Provided are a method, system, and article of manufacture for copying storage. Copy operations are performed on source storage units to copy to target storage units, wherein the copy operations create a consistent copy of the source storage units in the target storage units. While performing a copy operation to copy from one source storage unit to one target storage unit, a write operation is restricted from being performed on the one source storage unit, until the copy operations have been performed on the source storage units.

Abstract: Processor-based systems which may include non-volatile write-back cache and a disk drive may flush cache when the processor-based system is shut down. Flushing large cache to a disk drive may consume large amounts of time. Sequentially writing dirty cache lines during a system shutdown may alleviate the need to flush dirty cache lines and may require much less time.

Abstract: A memory tag mechanism creates a logical memory tag of a first length that corresponds to an I/O address of a second length. The memory tag is “logical” because it does not represent physical memory. When an I/O adapter device driver that expects an address of the first length is invoked, the memory tag is passed. When the I/O adapter device driver makes a call to the partition manager to convert the address of the first length (i.e., memory tag) to an I/O address of the second length, the partition manager detects that the passed address is a memory tag instead of a real address, and returns the corresponding I/O address. In this manner existing device drivers that expect addresses of the first length may be used for redirected DMA, which allows performing DMA operations directly from a shared I/O adapter in a hosting partition to memory in a hosted partition.

Abstract: Techniques to assure genuineness of data stored on a storage device are provided. The storage device includes a storage controller that conducts I/O operations and management operations. A description of management operations and corresponding timestamps are recorded to an operation log stored in a memory. The memory additionally stores an attribute for each storage volume of the storage device. Write access to each of the storage volumes is dependent on the attribute.

Abstract: Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.

Abstract: Under a hetero-environment in which different sorts of disk-systems are mixed with each other, a data guaranteeing operation can be carried out. When a cache controller of a local disk system receives a data writing request from a host computer the cache controller stores data into a local disk provided in a disk device group. The data received from the host computer is also transmitted to a remote disk system, and is stored in a remote disk. The data stored in the remote disk is immediately read and the data written in the remote disk is compared with the data written in the local disk. As a result, since a data guarantee operation on the remote side is processed by the local disk system instead of the remote disk system, a data guaranteeing operation when a remote copying operation is performed can be carried out even in the storage system under a hetero-environment.

Abstract: Apparatus and method for emulating a virtual machine within the physical memory space of a programmable processor using virtual functions having a format independent of the hardware architecture of the processor. The virtual functions are executed using an execution engine emulated in the processor. A symbol table maps the virtual functions to native functions in the memory space, and a gate call interface block accesses the symbol table and initiates execution of the corresponding native function in response to each executed virtual function. Execution of the corresponding native function operates to evaluate the concurrent execution of at least one other native function. In this way for example, standardized platform virtual code can be generated for a number of different types of processors and used to evaluate the native operational routines of each processor.

Abstract: Integrated search engine devices include a content addressable memory (CAM) core that is configured to support at least one database of searchable entries therein and a control circuit. The control circuit is configured to support reporting to a command host of data identifying entries that have been aged out of the at least one database and/or entries that have exceeded an activity-based aging threshold. The control circuit is further configured to support age reporting that is programmable on a per entry basis within the at least one database.

Abstract: A method and apparatus for efficient runtime memory access in a database is provided. A buffer pool is pre-allocated in cache. Buffers in the buffer pool are sized to accommodate average case queries and frequently executed queries. Buffers from the buffer pool are allocated to query working sets during runtime to reduce cache misses.

Abstract: Content addressable data storage and compression for semi-persistent computer memory for a database management system including providing a data structure that associates data identifiers and retrieval keys for memory blocks for storing in semi-persistent memory data from the database management system; searching for a segment of a chunk of data from the database management system that matches a memory block from semi-persistent memory; and if a matching segment is found: discarding the matching segment; storing in the data structure in the database management system a retrieval key for the matching segment in association with a data identifier; identifying an unmatched portion of the chunk that does not match the memory block; storing the unmatched portion semi-persistently in a free memory block from a file system; and storing in the data structure in the database management system a retrieval key for the unmatched portion in association with the data identifier.

Abstract: Transparent content addressable data storage and compression for a file system including providing a data structure that associates file identifiers and retrieval keys for memory blocks for storing file contents; storing in the data structure one or more file identifiers; providing a chunk of data comprising a quantity of input data of a file; retrieving a memory block from computer memory; searching for a segment of the chunk that matches the memory block; and if a matching segment is found: discarding the matching segment; providing a retrieval key for the memory block as a retrieval key for the matching segment; identifying an unmatched portion of the chunk that does not match the memory block; storing the unmatched portion; and providing a retrieval key for the unmatched portion.