Abstract: Special purpose heaps are created to store different classes of data to which different rules apply. A library of functions is provided which is designed to respect the different classes of rules that apply to the different heaps, by storing data only on a heap that is designated for use with the proper class of data, and by resisting the performance of actions on data in a heap that is inconsistent with the rules that apply to the heap. The use of plural heaps in this manner discourages programmer error in which an operation is performed on data that is inconsistent with the data, since the programmer would explicitly have to copy data from one heap to the other in order to perform the action. In one example, one heap is designated for the storage of secret data, and another heap is designated for general-purpose (non-secret) data.

Abstract: Processor-based systems may use more than one software routine or method to access a write-back cache. If the methods are inconsistent, the data in the write-back cache may be incoherent with a disk drive that is being cached. A method and apparatus for preserving coherent data in a write-back disk cache may include writing dirty cache lines to a disk drive and monitoring for disk write requests, prior to a disk driver loading.

Abstract: A method, an apparatus, and a computer program are provided for controlling a transmission enable (TX_ENA) signal. In Extreme Data Rate (XDR™) Dynamic Random Access Memories (DRAMs) or XDRAMS, there is a requirement that a TX_ENA signal remain logic high for a few cycles before data transmission, and, when TX_ENA transitions to logic low, TX_ENA remain logic low for a few cycles. However, maintaining this timing can be difficult with back-to-back writes. Therefore, additional logic is employed within XDRAM memory controllers to insure that TX_ENA does not violate system requirements by allowing TX_ENA to remain logic high between successive writes or when the system is devoid of commands.

Abstract: Embodiments of the present invention are directed to a method and apparatus for receiving an input/output (I/O) request from a host computer that specifies an operation to be performed on a content addressable storage (CAS) system and determining which operation is specified by the request before receipt of the I/O request by a content addressable storage system. In another embodiment, an I/O request from a host computer is received by a first CAS which determines if the request is to be processed by another CAS system. When it is determined that the request is to be processed by another CAS system, the first CAS system may forward the request to the other CAS system. In another embodiment, an appliance receives an I/O request from a host computer to perform an operation that accesses a unit of content. The appliance may set up a communication session between the host and a CAS system so that the unit of content may be transmitted between the host and the CAS system without passing through the appliance.

Abstract: A translation lookaside buffer has a plurality of entries in which address translation information obtained by translating a virtual address into a physical address is registered. The entries each have a priority bit that is set when the registered address translation information is required to be resident. At the time an entry substitution request occurs while the priority bits of all the entries are in a set state, a control circuit for controlling the translation lookaside buffer chooses as a subject of substitution an entry that has been least recently referred to, irrespective of states of the priority bits. This allows execution of the entry substitution with the priority bits in all of the entries being set.

Abstract: A method for adaptation of data organization by a data storage system controller is disclosed. Data organization in a data storage system is adapted according to varying workload profiles and system constraints. The data storage system also consists of a plurality of data storage units. On receipt of a request to write data, various workload and data storage system parameters are determined. On the basis of these parameters, target data storage units and appropriate data organization schemes are optimally selected. In the case where the volume of data to be written is less than a threshold value, a RAID organization scheme is preferred. In this scheme the data is written to the selected drives simultaneously. In the case where the volume of data to be written is more than the threshold value, a power managed RAID organization scheme, where all data drives need not be simultaneously powered on, is used.

Abstract: Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Abstract: A media processing device uses an external storage device. The media processing device includes a storage device access module, an information source, a program memory, a system memory, a signal processor, a user interface and a system controller. The system controller accesses the external storage device, reads file information, and constructs contents to be displayed. When the system controller receives a command to select a media file, the system controller accesses the external storage device, searches for the selected media file, reads data of the searched media file, copies the read data, and provides the copied data to be decoded. When the system controller receives a commend to encode a signal, the system controller controls the signal processor to encode the input signal into media data, constructs a media file from the encoded media data, positions the media file, and copies the constructed media file when the external storage device is accessible through the storage device access module.

Abstract: The generation and selection of addresses to be employed in a verification environment are tightly coupled to ensure that the addresses a user desires to be selected have been generated. Addresses are generated based on one or more defined selection attributes. The generated addresses are maintained in a database structure that also includes any attributes associated with the addresses. At least one address is selected from the database structure via a filter and forwarded to a component under test.

Abstract: Methods and apparatus are provided for handling events such as faults and resets. Specialized circuitry or hardware is provided within a processor to invalidate the cache line associated with the processor cache reset address. Based on the invalided state of the cache reset address line, the processor obtains new instructions from data memory. The new instructions can be configured to invalidate the remaining cache lines using software mechanisms.

Abstract: A circuit external to a memory controller in a processing system places a dynamic random access memory into a self-refresh state in response to a predetermined condition associated with a power-down or reset event.

Abstract: Signal elements are mapped to a limited range of identifiers by emulating a “virtual” space of identifiers larger than the real limited space of identifiers. The larger virtual identifier space is implemented by an intermediate memory, which provides storage of identifiers assigned from the real space of identifiers. For each signal element to be mapped to an identifier, the intermediate memory is addressed by a hash value calculated from at least part of the signal element, thus allowing access to an identifier. The larger virtual space gives a better distribution of signal elements to the identifiers; and reduces the probability of different signal elements being mapped to the same identifier (“clashing”). For an efficient reduction of the clashing probability, identifiers with a low probability of being active are assigned to the intermediate memory to represent new signal elements.

Abstract: An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.

Abstract: A diskarray system has a diskarray controller and a plurality of disk devices. Each of the disk devices has a media, a head, and a head position controller. The diskarray controller performs online data check operation, and stops the online data check operation over the disk device at first predetermined timing. After stopping the online data check operation, the diskarray controller issues an unload enable command to the disk device so as to move the head to a position different from positions at which the head reads or writes data from or to the media. The head position controller of the disk device moves the position of the head on the basis of the received unload enable command.

Abstract: A method for returning a logical volume which is part of a redundant data storage system to on-line status following a disk failure within the logical volume during the time when another of that volume's disks is unavailable as a result of having its firmware updated, as an example. Data which would otherwise be changed in the logical volume due to host write requests is directed to a logging facility within the data storage system, but outside of the logical volume undergoing upgrade.

Abstract: A storage apparatus is provided in which the data amount of transfer data to a secondary disk controller from a primary disk controller at the event of remote copying can be reduced, and data integrity also can be assured. According to the storage apparatus, in the primary disk controller, overwriting update data in same records during a specified time between a preset first base point and a preset second base point on the update data that are stored in the second area of the cache memory and that are to be transferred to the secondary disk controller; and in the secondary disk controller, handling the update data between the first base point and the second base point as real data having consistency.

Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required.

Abstract: Apparatus and method to implicitly transmit a command to close a row of memory cells within a memory device as part of the transmission of an activate command to open another row of memory cells within the memory device.

Abstract: A virtualizer module/element and a networked storage controller architecture with a virtualization layer that includes virtualizer modules. The virtualizer modules contain storage controller functionality as well as a cache subsystem. The virtualizer module processes primary data commands received from a host processor to determine if the cache subsystem of the virtualizer can service the data request or if it should be sent to a command mapper to retrieve the data from a downstream storage element. The cache subsystem of the virtualizer module thus enables reduced latency in the networked storage system as well as better management of storage devices and resources. The virtualizer module also facilitates predictive reads and read-ahead operations as well as coalesced write requests to a given storage device in order to increase system performance and storage device longevity.

Abstract: To improve the convenience of using a memory module, there are provided indicator elements corresponding to types of access to semiconductor memory. The indicator elements are configured to correspond to the access type and indicate the frequency of this type of access to the semiconductor memory. The indicator elements are also configured to indicate the frequency of access to the semiconductor memory and hold an indication corresponding to the maximum frequency of the access. Furthermore, the indicator elements are configured to indicate the frequency of access to the semiconductor memory when a connection terminal 22 is connected to a motherboard connector 91 and a memory module connection terminal 82 is connected to a connector 23.