Abstract: A method, an apparatus, and a computer program are provided for controlling a transmission enable (TX_ENA) signal. In Extreme Data Rate (XDR™) Dynamic Random Access Memories (DRAMs) or XDRAMS, there is a requirement that a TX_ENA signal remain logic high for a few cycles before data transmission, and, when TX_ENA transitions to logic low, TX_ENA remain logic low for a few cycles. However, maintaining this timing can be difficult with back-to-back writes. Therefore, additional logic is employed within XDRAM memory controllers to insure that TX_ENA does not violate system requirements by allowing TX_ENA to remain logic high between successive writes or when the system is devoid of commands.

Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.

Abstract: A trusted data store is provided for use with a trusted element of a trusted operating system on a computing machine. In the trusted data store, a storage medium stores data in a pre-determined arrangement, where the data includes trusted data from the trusted element of the trusted operating system on the computing machine. An access controller writes data to and reads data from the storage medium, and a trust controller is interposed between the computing machine and the access controller. The trust controller allows only the trusted element to perform operations on the trusted data thereof on the storage medium.

Abstract: A file memory stores data corresponding to identifiers of an allocated area in an identifier space. A first memory stores a basis position of the allocated area in the identifier space. A second memory stores a weight of the storage apparatus as a performance degree. A first decision unit decides a space width to divisionally allocate the identifier space with another storage apparatus by using the weight and a weight of another storage apparatus. Another storage apparatus allocates a neighboring area of the allocated area in the identifier space. A second decision unit decides the allocated area of an area between the basis position and a basis position of the neighboring area in the identifier space by using the space width.

Abstract: In one aspect the invention provides a signal bearing medium tangibly embodying a program of machine-readable instructions that are executable by a digital processing apparatus to perform operations to determine a maintenance fee for a data storage system. The operations include monitoring at least one data storage device during operation of the data storage system to determine a duty cycle and determining a current value of the maintenance fee based at least in part on the determined duty cycle. In a further disk drive-based embodiment the operations may include, or be instead, determining a disk drive redundancy configuration of disk drives of a data storage system. The operations then compare the determined duty cycle to a threshold value and assert a redundancy configuration change signal based on the result of the comparison. For a RAID configuration embodiment having a RAID level, the asserting operation asserts a RAID level change signal based on the result of the comparison.

Abstract: An apparatus and method for ensuring coherency of instructions within stages of the pipeline microprocessor. The apparatus includes instruction cache management logic and synchronization logic. The instruction cache management logic receives an address corresponding to a next instruction to be fetched, and detects that a part of a memory page corresponding to the next instruction cannot be freely accessed without checking for coherency of the instructions within the part of the memory page and, upon detection, provides the address. The synchronization logic receives the address from the instruction cache management logic. The synchronization logic directs data cache management logic to check for coherency of the instructions within the part of the memory page, and, if the instructions are not coherent within the part of the memory page, the synchronization logic directs the pipeline microprocessor to stall a fetch of the next instruction until the stages of the pipeline.

Abstract: A memory module includes at least one memory chip arranged on the memory module. Information about the memory module and/or the at least one memory chip arranged on the memory module can be stored directly on the memory chip, making use of a suited element, fuses or flip-flops, for example. A memory chip contains such an element for containing information relating to the memory chip and/or a memory module with which the memory chip is compatible, wherein the information containing element can be read out by means of an external processor.

Abstract: A method of detecting sequential data transfer requests, includes determining whether a first data transfer request crosses a boundary address, and, if it does, determining if the first data transfer request may be indicated as combinable with subsequent data transfer requests. The method may also include determining whether a previous data transfer request has been indicated as combinable, and if it has been indicated as combinable, determining that a new data transfer request is addressed adjacent to the previous data transfer request.

Abstract: A storage device such as a disk drive is provided with a lateral storage director. The lateral storage director is capable of self-assessing the status of the storage device. The lateral storage director also enables one storage device to transfer data files to another storage device over a communications link without the supervision of a host computer.

Abstract: A semiconductor system according to an embodiment of the present invention comprises a shared memory; a plurality of processing units each of which designates a memory size and a memory address, and which uses the shared memory; an address allocation unit which allocates memory addresses having the memory size designated by the each processing unit to the processing unit; and an address conversion unit which converts the memory address designated by the each processing unit into one of the memory addresses allocated to the processing unit, the converted memory address being including in the shared memory and being accessed by the processing unit.

Abstract: An integrated circuit device includes a processing component and a cache, which is arranged to store data for use by the processing component responsively to an addressing scheme based on memory addresses having an address length of ml bits. First and second buses are coupled between the processing component and the cache, the buses having bus widths of n1 and n2 bits, respectively, such that n1<m1. The processing component and the cache each include a respective address bus expander coupled to the first bus in order to compact at least some of the memory addresses for transmission over the first bus so that each of the at least some memory addresses is transmitted over the first bus in one cycle of the first bus.

Abstract: A method to rebuild an NVS image is disclosed. The method provides information to a first cluster of an information storage and retrieval system, and writes that information to a non-volatile storage device disposed in a second cluster. Upon losing utility power to all or part of the information storage and retrieval system, the method provides back-up power to a processor and a data cache, and determines if the information written to the second non-volatile storage device is accessible. If the information written to the second non-volatile storage device is accessible, then the method copies the image of that second non-volatile storage device to an external storage device. If the information written to said second non-volatile storage device is not accessible, then the method creates a virtual NVS image using the information disposed in a local data cache, and copies that virtual NVS image to an external storage device.

Abstract: A storage system maintains a journal of journal entries and at lease one snapshot of one or more data volumes. By assigning a unique sequence number to journal and snapshot, it is easy to find a journal which can be applied to the snapshot. A technique is described for detecting an overflow condition of running out of journal space and recovering the journal space.

Abstract: Embodiments of the present invention are directed to a method and apparatus for receiving an input/output (I/O) request from a host computer that specifies an operation to be performed on a content addressable storage (CAS) system and determining which operation is specified by the request before receipt of the I/O request by a content addressable storage system. In another embodiment, an I/O request from a host computer is received by a first CAS which determines if the request is to be processed by another CAS system. When it is determined that the request is to be processed by another CAS system, the first CAS system may forward the request to the other CAS system. In another embodiment, an appliance receives an I/O request from a host computer to perform an operation that accesses a unit of content. The appliance may set up a communication session between the host and a CAS system so that the unit of content may be transmitted between the host and the CAS system without passing through the appliance.

Abstract: Embodiments of the present invention are directed to a method and apparatus for receiving an input/output (I/O) request from a host computer that specifies an operation to be performed on a content addressable storage (CAS) system and determining which operation is specified by the request before receipt of the I/O request by a content addressable storage system. In another embodiment, an I/O request from a host computer is received by a first CAS which determines if the request is to be processed by another CAS system. When it is determined that the request is to be processed by another CAS system, the first CAS system may forward the request to the other CAS system. In another embodiment, an appliance receives an I/O request from a host computer to perform an operation that accesses a unit of content. The appliance may set up a communication session between the host and a CAS system so that the unit of content may be transmitted between the host and the CAS system without passing through the appliance.

Abstract: One aspect of the invention is a method for ensuring consistency of a group, which for example, includes receiving a first list that identifies objects in the group, and gathering for at least one attribute, the value of the attribute for each object in the first list. The first list, and the attribute values gathered in the gathering operation, are stored to create a first snapshot. This example also includes receiving a second list that identifies objects that are in the group after at least part of a task is performed, and the value after at least part of the task is performed of the at least one attribute for each object identified in the second list. The second list and the received attribute values are stored to create a second snapshot, which is compared with the first snapshot.

Abstract: Various embodiments of systems and methods for performing accumulation operations on block operands are disclosed. In one embodiment, an apparatus may include a memory, a functional unit that performs an operation on block operands, and a cache accumulator. The cache accumulator is configured to provide a block operand to the functional unit and to store the block result generated by the functional unit. The cache accumulator is configured to provide the block operand to the functional unit in response to an instruction that uses an address in the memory to identify the block operand. Thus, the cache accumulator behaves as both a cache and an accumulator.

Abstract: A translation lookaside buffer has a plurality of entries in which address translation information obtained by translating a virtual address into a physical address is registered. The entries each have a priority bit that is set when the registered address translation information is required to be resident. At the time an entry substitution request occurs while the priority bits of all the entries are in a set state, a control circuit for controlling the translation lookaside buffer chooses as a subject of substitution an entry that has been least recently referred to, irrespective of states of the priority bits. This allows execution of the entry substitution with the priority bits in all of the entries being set.

Abstract: A storage system having multiple I/O interface ports is configured to detect a failed communication condition at a port. The storage system is configured to then attempt communication using a port configuration of another port that also exhibits a failed communication condition. If communication is established, the port is reconfigured using the configuration of the other port.

Abstract: A method for adaptation of data organization by a data storage system controller is disclosed. Data organization in a data storage system is adapted according to varying workload profiles and system constraints. The data storage system also consists of a plurality of data storage units. On receipt of a request to write data, various workload and data storage system parameters are determined. On the basis of these parameters, target data storage units and appropriate data organization schemes are optimally selected. In the case where the volume of data to be written is less than a threshold value, a RAID organization scheme is preferred. In this scheme the data is written to the selected drives simultaneously. In the case where the volume of data to be written is more than the threshold value, a power managed RAID organization scheme, where all data drives need not be simultaneously powered on, is used.