Abstract: An invention is disclosed for automatically preparing removable media for content, such as by automatically formatting media such as CDs and DVDs. A drive type is determined for a drive present on a computer system. The drive type defines characteristics of the drive. In addition, a media type is detected for removable media, such as a compact disc or floppy disk, present in the drive. Similar to the drive type, the media type defines characteristics of the removable media. Based on the drive type and media type, the removable media is automatically prepared for content in response to receiving a request to write to the removable media.

Abstract: A method of operation within a content addressable memory (CAM) device. An input data word having a plurality of data bits and a plurality of mask bits is received in the CAM device. An encoded data word is generated based, at least in part, on states of the mask bits within the input data word. A write data word is selected from a group of data words that includes at least the input data word and the encoded data word. The write data word is stored within a row of CAM cells within the CAM device.

Abstract: A method for returning a logical volume which is part of a redundant data storage system to on-line status following a disk failure within the logical volume during the time when another of that volume's disks is unavailable as a result of having its firmware updated, as an example. Data which would otherwise be changed in the logical volume due to host write requests is directed to a logging facility within the data storage system, but outside of the logical volume undergoing upgrade.

Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required.

Abstract: A storage apparatus is provided in which the data amount of transfer data to a secondary disk controller from a primary disk controller at the event of remote copying can be reduced, and data integrity also can be assured. According to the storage apparatus, in the primary disk controller, overwriting update data in same records during a specified time between a preset first base point and a preset second base point on the update data that are stored in the second area of the cache memory and that are to be transferred to the secondary disk controller; and in the secondary disk controller, handling the update data between the first base point and the second base point as real data having consistency.

Abstract: Apparatus and method to implicitly transmit a command to close a row of memory cells within a memory device as part of the transmission of an activate command to open another row of memory cells within the memory device.

Abstract: A virtualizer module/element and a networked storage controller architecture with a virtualization layer that includes virtualizer modules. The virtualizer modules contain storage controller functionality as well as a cache subsystem. The virtualizer module processes primary data commands received from a host processor to determine if the cache subsystem of the virtualizer can service the data request or if it should be sent to a command mapper to retrieve the data from a downstream storage element. The cache subsystem of the virtualizer module thus enables reduced latency in the networked storage system as well as better management of storage devices and resources. The virtualizer module also facilitates predictive reads and read-ahead operations as well as coalesced write requests to a given storage device in order to increase system performance and storage device longevity.

Abstract: Techniques to assure genuineness of data stored on a storage device are provided. The storage device includes a storage controller that conducts I/O operations and management operations. A description of management operations and corresponding timestamps are recorded to an operation log stored in a memory. The memory additionally stores an attribute for each storage volume of the storage device. Write access to each of the storage volumes is dependent on the attribute.

Abstract: To improve the convenience of using a memory module, there are provided indicator elements corresponding to types of access to semiconductor memory. The indicator elements are configured to correspond to the access type and indicate the frequency of this type of access to the semiconductor memory. The indicator elements are also configured to indicate the frequency of access to the semiconductor memory and hold an indication corresponding to the maximum frequency of the access. Furthermore, the indicator elements are configured to indicate the frequency of access to the semiconductor memory when a connection terminal 22 is connected to a motherboard connector 91 and a memory module connection terminal 82 is connected to a connector 23.

Abstract: A memory controller, such as a SDRAM controller, forms a queue of memory access requests to maximize efficient use of the bandwidth of the memory data bus. More specifically, the SDRAM controller pre-calculates the number of data bursts required to retrieve all the required data from the SDRAM, and the starting address for each of the data bursts, and queues the access requests for these data bursts such that the data bursts may be retrieved without incurring the usual read latency for each data burst.

Abstract: Briefly, in accordance with one embodiment of the invention, applications may be dynamically relocated from one flash memory device to another flash memory device based on application usage data. Monitoring of application usage may be continuous, and the application usage data may be updated as application usage changes over time.

Abstract: A method and apparatus are provided for computer memory protection and verification. In one example, the apparatus is a secure memory device (SMD) including means to independently read the program memory device and compute and store a signature or other means of verification of binary content of the program memory device, means to compare binary program memory content to binary program memory content stored in the program memory device, and means to disable reading and writing of the program memory device if predetermined conditions do not occur. A previously stored signature of program memory content may be used as means of verification of previous program memory content. A secure memory device may be constructed as a single securely enclosed unit that is tamperproof and that has electrical connections available only for purpose of connection with an apparatus that accepts a program memory.

Abstract: In general, techniques are described for initializing a memory module in accordance with a programmable initialization sequence. A memory controller, for example, includes a programmable computer-readable medium that stores configuration data to control initialization of one or more memory modules. The memory controller includes an initialization control unit that outputs a sequence of commands to initialize the memory modules in accordance with the configuration data. The initialization control unit may select the sequence of commands from a set of predefined initialization sequences based on the configuration data.

Abstract: A method for adaptation of data organization by a data storage system controller is disclosed. Data organization in a data storage system is adapted according to varying workload profiles and system constraints. The data storage system also consists of a plurality of data storage units. On receipt of a request to write data, various workload and data storage system parameters are determined. On the basis of these parameters, target data storage units and appropriate data organization schemes are optimally selected. In the case where the volume of data to be written is less than a threshold value, a RAID organization scheme is preferred. In this scheme the data is written to the selected drives simultaneously. In the case where the volume of data to be written is more than the threshold value, a power managed RAID organization scheme, where all data drives need not be simultaneously powered on, is used.

Abstract: A method and apparatus for generating bits for a diagnostic routine of a memory subsystem. A memory device may be divided into n subdivisions of m bits each. Alternatively, n memory devices may each have m bits (in width). The system may also have a cache line having a certain number of check words. A diagnostic routine may begin with the generating one of 2m bit patterns and assigning m bits of the generated bit pattern to one of the check words in the cache line. Each of the m bits assigned to the check word in the cache line may have the same logic value. However, each bit of the n subdivisions may be associated with a different check word in the cache line with respect to other bits of the subdivision. The method may be repeated for each of the 2m bit patterns that may be generated.

Abstract: Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory arrangements connected to the buffer chip are provided. A buffer circuit may receive first initialization data specifying a first set of available memory arrangement addresses and associate one or more of the first set of available memory arrangement addresses with the one or more memory arrangements connected to the buffer chip. The buffer circuit may also generate second initialization data specifying the set of available memory arrangement addresses available after the association. The second initialization data may be transmitted to another buffer circuit for use in address allocation or back to a memory access control unit.

Abstract: A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

Abstract: A system is configured to selectively block peripheral accesses to system memory. The system includes a secure execution mode (SEM)-capable processor configured to operate in a trusted execution mode. The system also includes a system memory including a plurality of addressable locations. The system further includes a memory controller that may determine a source of an access request to one or more of the plurality of locations of the system memory. The memory controller may further allow the access request to proceed in response to determining that the source of the access request is the SEM-capable processor.

Abstract: A method, system and apparatus for improving the useful life of non-volatile memory devices such as flash memory. The present wear-leveling technique advantageously improves the overall useful life of a flash memory device by strategically moving inactive data (data that has been infrequently modified in the recent past) to the memory blocks that have experienced the most wear since the device began operation and by strategically moving active data to the memory blocks that have experienced the least wear. In order to efficiently process and track data activity and block wear, vectors of block-descriptor pointers are maintained. One vector is sorted in decreasing order of overall block erase/write activity (block-wear indicator), whereas the other vector is sorted in increasing order of the number of times a block has been erased since the last wear-leveling event occurred (activity indicator for the data stored in the block).

Abstract: Disclosed are a system, a method, and an article of manufacture to provide for configuring an automated data storage library having one or more storage frames that operate with different types of data storage media. The automated data storage library is configured to operate with sequential storage shelf addresses assigned to consecutive storage frames that use the same type of data storage media. The storage frames that operate with different types of data storage media may be physically assembled in any order. The automated data storage library may be expanded by attaching storage frames that operate with different types of data storage media in any order while maintaining sequential storage shelf addresses that span across multiple library frames.