Abstract: A data sharing method and disk control device are ideal for running applications to process large amounts of data on remote computers in the same manner as in a database system. A disk control device contains a management table for showing the relation between a remote access identifier, a remote disk control device identifier, and command transfer control information for the remote disk control device to the disk identifier used by the host device, When a write command to write data on a designated disk is received from the host computer, the disc controller executes both a write process for writing data on a designated disk and a command transfer process for transferring a write command to the remote disk controller in accordance with command transfer control information in the management table.

Abstract: A system, program storage device, and method of optimizing data placement on a storage device, the method comprising establishing a specified time constraint for which the storage device is to delete data stored thereon; dividing a data object into a plurality of data bits; programming a block of data and the data bits with a logic operand if the storage device is incapable of deleting the data within the specified time constraint; creating an encoded block of data from the programmed block of data and the data bits; organizing the encoded block of data and the data bits in the storage device according to data deletion requirements; and removing the data bits from the storage device if the data bits are organized within a specified data deletion requirement, wherein the data bits are removed using a data shredding process, and wherein the logic operand comprises an exclusive-or (XOR) operator.

Abstract: It is an object of the present invention to conduct data transfer or data copying between a plurality of storage systems, without affecting the host computer of the storage systems. Two or more auxiliary storage systems 100B, 100C are connected to a primary storage system 100A connected to a host device 180. The auxiliary storage systems 100B, 100C read journals of data update from the primary storage system 100A at respective independent timings, save the journals in prescribed logical volumes JNL 2, JNL 3, produce copying of the data present in the primary storage system 100A based on the journals present in the logical volumes JNL 2, JNL 3 at the independent timings, and save the copies in auxiliary logical volumes COPY 1, COPY 3. The primary storage system 100A holds the journals till both auxiliary storage systems 100B, 100C read the journals and restore. The timing of journal read can be controlled according to the journal quantity, processing load, and the like.

Abstract: The generation and selection of addresses to be employed in a verification environment are tightly coupled to ensure that the addresses a user desires to be selected have been generated. Addresses are generated based on one or more defined selection attributes. The generated addresses are maintained in a database structure that also includes any attributes associated with the addresses. At least one address is selected from the database structure via a filter and forwarded to a component under test.

Abstract: Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Abstract: A media processing device uses an external storage device. The media processing device includes a storage device access module, an information source, a program memory, a system memory, a signal processor, a user interface and a system controller. The system controller accesses the external storage device, reads file information, and constructs contents to be displayed. When the system controller receives a command to select a media file, the system controller accesses the external storage device, searches for the selected media file, reads data of the searched media file, copies the read data, and provides the copied data to be decoded. When the system controller receives a commend to encode a signal, the system controller controls the signal processor to encode the input signal into media data, constructs a media file from the encoded media data, positions the media file, and copies the constructed media file when the external storage device is accessible through the storage device access module.

Abstract: A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of operation codes designated by the address generation code of one of the instructions and of the content of one address register selected from said address registers. Each address generation code defines an operation code to be sent to the calculation circuit. Each of the address registers is further associated with a configuration register designated at the same time as the address register by the address generation code, and each of the configuration registers contains a set of predefined operation codes, each adapted to command a predetermined calculation operation in the calculation circuit.

Abstract: An instruction virtual address space includes only virtual addresses corresponding to physical addresses of address areas of a physical address space storing pages of only instructions. A data virtual address space includes only virtual addresses corresponding to physical addresses of address areas of the physical address space storing pages of only data. The instruction and data virtual address spaces use duplicated virtual addresses. Instruction and data address translation units translate virtual addresses of the instruction and data virtual address spaces into physical addresses of the single physical address space. A data access efficiency and an instruction execution speed can be improved.

Abstract: Methods and apparatus are provided for handling events such as faults and resets. Specialized circuitry or hardware is provided within a processor to invalidate the cache line associated with the processor cache reset address. Based on the invalided state of the cache reset address line, the processor obtains new instructions from data memory. The new instructions can be configured to invalidate the remaining cache lines using software mechanisms.

Abstract: A scrambling operation is used to space apart the grants that a communication circuit receives during a period of time, such as 512 arbitration periods. An operator can enter the number of arbitration periods that a communication circuit is to receive in blocks of sequential logical address ranges. The logical addresses are then changed to physical addresses that are spaced apart, thereby significantly reducing the buffering required by the communication circuit.

Abstract: A circuit external to a memory controller in a processing system places a dynamic random access memory into a self-refresh state in response to a predetermined condition associated with a power-down or reset event.

Abstract: Signal elements are mapped to a limited range of identifiers by emulating a “virtual” space of identifiers larger than the real limited space of identifiers. The larger virtual identifier space is implemented by an intermediate memory, which provides storage of identifiers assigned from the real space of identifiers. For each signal element to be mapped to an identifier, the intermediate memory is addressed by a hash value calculated from at least part of the signal element, thus allowing access to an identifier. The larger virtual space gives a better distribution of signal elements to the identifiers; and reduces the probability of different signal elements being mapped to the same identifier (“clashing”). For an efficient reduction of the clashing probability, identifiers with a low probability of being active are assigned to the intermediate memory to represent new signal elements.

Abstract: A process, apparatus, and system stores data check information on an electronic storage medium that uses standard sector data field sizes. The check information may include a cyclic redundancy check (CRC), a logical block address (LBA), a longitudinal redundancy check (LRC), state information, a sequence number, or other information to identify data state, misplacement, or corruption. The check information, instead of being appended to the data within the data sector, may be stored in an independent check sector. The check information corresponding to multiple data sectors may also be aggregated and stored in a single check sector. The process or apparatus may be incorporated in a storage system controller, a RAID controller, a software SCSI stack in a computer, an operating system, a storage device driver, or another appropriate application that interfaces with standard and commodity storage system components.

Abstract: Methods and apparatus for allow different mapping implementations, including a many-to-one logical to physical block mapping, to be used within a memory system are disclosed. According to one aspect of the present invention, a method for mapping a plurality of logical blocks to a physical block includes identifying a first logical block meets at least one criterion. The method also includes identifying a second logical block which is substantially complementary to the first logical block, and providing contents associated with the first logical block and contents associated with the second logical block to the physical block.

Abstract: A microprocessor apparatus is provided that enables exclusive allocation and renaming a cache line. The apparatus includes translation logic and execution logic. The translation logic translates an allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first cache line in an exclusive state and to copy the contents of a second cache line into the first cache line. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the first cache line in the exclusive state. Upon granting of exclusive rights, the execution logic copies the contents of the second cache line into the first cache line.

Abstract: A method and apparatus for programming nonvolatile (flash) memory in a microcontroller. A nonvolatile memory in the microcontroller is connected via data, address and control signal paths to a processor internal to the microcontroller. These paths are not available to the outside world. In order to program the nonvolatile memory, a tester/programmer provides instructions to a test/control interface and the actual programming of the nonvolatile memory is carried out under control of a supervisory ROM forming a part of the microcontroller storing instructions which are carried out by the processor.

Abstract: Performing selective update of a content addressable memory (CAM) following restart of an access control module (ACM) at a network node involves maintaining a restart CAM entry database in shared memory. When the ACM restarts, instead of reentering all CAM entries into the CAM or reading the contents of the CAM, the ACM only updates the CAM with the entries that were modified while the ACM was offline, prior to restart.

Abstract: A diskarray system has a diskarray controller and a plurality of disk devices. Each of the disk devices has a media, a head, and a head position controller. The diskarray controller performs online data check operation, and stops the online data check operation over the disk device at first predetermined timing. After stopping the online data check operation, the diskarray controller issues an unload enable command to the disk device so as to move the head to a position different from positions at which the head reads or writes data from or to the media. The head position controller of the disk device moves the position of the head on the basis of the received unload enable command.

Abstract: An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.

Abstract: An address decoding method and related apparatus for deciding which section of a memory device a given address belongs. The memory device has a plurality of sections, each section has a plurality of memory units, and each memory unit has a unique address. The method includes: comparing some specific bits of the given address with predetermined values for deciding which section the given address belongs.