Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

Abstract: A memory system includes a memory group including a plurality of memory devices having two or more different types; and a controller configured to control data input and output for the memory group, wherein the controller includes a scrubbing controller configured to collect health information to which a deterioration degree for each of the plurality of memory devices is reflected and determine a scrubbing interval for each of the plurality of memory devices based on the health information, the scrubbing interval being reduced in proportion to the deterioration degree.

Abstract: A data processing apparatus 2 includes a cache memory 8 for storing data items to be accessed. Coherency control circuitry 20 controls coherency between data items stored within the cache memory and one or more other copies of the data items stored outside the cache memory. A data access buffer 6 buffers a plurality of data access to respective data items stored within the cache memory. Access control circuitry 20 is responsive to coherency statuses managed by the coherency control circuitry for the plurality of data items to be subject to data access operations to be performed together atomically as an atomic set of data accesses to ensure that the coherency statuses for all of these data items permit all of the atomic set of data accesses to be performed within the cache memory before the set of atomic data accesses are commenced.

Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: maintaining first management information for identifying a first management unit in the rewritable non-volatile memory module; collecting first valid data from the first management unit according to the first management information without reading first mapping information from the rewritable non-volatile memory module in a data merge operation, and the first mapping information includes logical-to-physical mapping information related to the first valid data; and storing the collected first valid data into a recycling unit.

Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.

Abstract: A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation that specifies a target address, determines whether or not the cache memory has coherence ownership of the target address. Based on determining the cache memory has coherence ownership of the target address, the snoop logic services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores until conclusion of a second flush/clean memory access operation that specifies the target address.

Abstract: A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a flush or clean memory access operation of an initiating coherence participant, determines whether the directory indicates the cache memory has coherence ownership of a target address of the request. Based on determining the directory indicates the cache memory has coherence ownership of the target address, the snoop logic provides a coherence response to the request that causes coherence ownership of the target address to be transferred to the initiating coherence participant, such that the initiating coherence participant can protect the target address against conflicting requests.

Abstract: An electronic card includes a support substrate, a plurality of storage devices on the support substrate, and a plurality of controllers on the support substrate to manage access of the corresponding plurality of storage devices, wherein the plurality of controllers and the plurality of storage devices are arranged to store data according to a Redundant Array of Independent Disks (RAID) mode.

Abstract: Systems, apparatuses, and methods related to tokens to indicate completion of data storage to memory are described. An example method may include storing a number of data values by a first page in a first row of an array of memory cells responsive to receipt of a first command from a host, where the first command is associated with an open transaction token, and receiving a second command from the host to store a number of data values by a second page in the first row. The method may further include sending a safety token to the host to indicate completion of storing the number of data values by the second page in the first row.

Abstract: The present invention provides a data protection method and storage device. The data protection method includes: (A): during an initial period after the storage device is connected to a host, detecting the storage device and determining whether the storage device needs to be performed with data protection; (B): when the storage device needs to be performed with data protection in Step (A), modifying a predetermined writing destination that the host writes data to a storage unit of the storage device, to make the data from the host be written to another writing destination rather than being written to said writing destination; or writing the data from the host into a control chip or a bridge chip of an inner memory or an inner register, rather than writing the data from the host into the storage device; and (C): reporting to the host that the writing operation is completed.

Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.

Abstract: A memory system includes a memory controller. The memory controller includes a program history manager for managing a program history of a first memory unit including a plurality of sub-units of which write protection mode is set; and a memory unit manager for selecting, based on the program history, at least one sub-unit on which a program operation is not performed during a set period among the plurality of sub-units, and releasing the write protection mode of the at least one selected sub-unit.

Abstract: Initializing a data structure for use in predicting table of contents (TOC) pointer values. A request to load a module is obtained. Based on the loaded module, a pointer value for a reference data structure is determined. The pointer value is stored in a reference data structure tracking structure, and used to access a variable value for a variable of the module.

Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.

Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.

Abstract: Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

Abstract: A storage system and method for determining ecosystem bottlenecks and suggesting improvements are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller comprises a plurality of hardware components, at least one of the hardware components configured to communicate with the memory; a plurality of busses connecting the hardware components; a plurality of monitors, wherein each monitor is configured to collect information on utilization of a respective one of the plurality of busses; and a processor in communication with the plurality of monitors, wherein the processor is configured to: analyze the information on utilization of the busses collected from the plurality of monitors; and provide a result of the analysis to a device external to the storage system.

Abstract: A system of handling electronic information having a virtually tagged cache having a directory and a plurality of entries containing data, the directory containing multiple entries, each entry configured to comprise at least a virtual address and one of a plurality of context tags, wherein each context tag is an encoding for one of a plurality of layers of address space; a context tag table having a plurality of entries, each entry configured to map one of the plurality of context tags to one of the plurality of layers of space; and a scratch register containing a current context tag for a current layer of address space on which the processor is operating. The virtually tagged cache is configured to preserve information in the virtually tagged cache when performing a context switch in the system.