Abstract: Systems, methods, and computer program products for buffer management in a memory device are provided. Aspects include receiving, by a controller, a request to write a first data to a memory device, analyzing, by the controller, the first data to determine a data type for the first data, obtaining, by the controller, one or more input parameters associated with the memory device, and based on at least one of the one or more input parameters exceeding a first threshold, writing the first data to a write credit buffer.

Abstract: The present disclosure relates to storing data in a computer system. The computer system comprising a main memory coupled to a processor and a cache hierarchy. The main memory comprises a predefined bit pattern replacing existing data of the main memory. Aspects include storing the predefined bit pattern into a reference storage of the computer system. At least one bit in a cache directory entry of a first cache line of the cache hierarchy can be set. Upon receiving a request to read the content of the first cache line, the request can be redirected to the predefined bit pattern in the reference storage based on the value of the set bit of the first cache line.

Abstract: A mechanism is provided for destaging one or more data files in a volatile memory using a set of heat registers associated with each data file. Responsive to receiving a notification indicating that free space within the volatile memory has fallen below a predetermined threshold, a rule is implemented, based on values associated with the set of heat registers assigned to each data file, to identify a data file to move to a non-volatile memory, where the set of heat registers comprises a content heat register, an access heat register, and a metadata heat register. The data file is moved to the nonvolatile memory. Responsive to determining that the free space fails to have risen above the predetermined threshold, the operations are repeated until the free space rises above the predetermined threshold at which time the set of heat registers assigned to the data files that were moved are deassigned.

Abstract: Soft read suspend schemes for a memory system reduce overall command latency and improve QoS of the memory system, which includes a memory device and a memory controller. The memory controller controls the memory device to perform, in response to a command, a hard read to generate hard information for hard decoding, and predict whether soft decoding of the data is to be performed, and if so, how many soft reads are to be performed. When hard decoding fails and soft decoding and at least one soft read is to be performed, the memory device is controlled to perform an initial soft read to generate soft information for soft decoding, predict whether, and if so, how many, subsequent soft reads are to be performed, and determine whether to perform a first subsequent soft read on the data based on the prediction.

Abstract: One embodiment facilitates operation of non-volatile memory. During operation, the system determines, by a flash translation layer module, a physical block address associated with a first request which indicates data to be read, wherein the non-volatile memory is divided into separate physical zones, wherein the physical block address is associated with a first physical zone, and each separate physical zone has a dedicated application to read or write data thereto. The system obtains a free page frame in a volatile memory by writing data from a cold page in the volatile memory to a second physical zone, wherein a cold page is a page with a history of access which is less than a predetermined threshold. The system loads, based on the physical block address, data from the non-volatile memory to the free page frame. The system executes the request based on the data loaded into the free page frame.

Abstract: A system includes a memory and at least one processor to continually analyze at least one of metrics, events, and conditions in a computer network, under normal operating conditions in the computer network, obtain a first level of data from at least one hardware device in the computer network, detect that one of a condition and an event has occurred in the computer network, automatically transmit an instruction to modify the first level of data obtained from the at least one hardware device to a second level of data more robust than the first level of data when one of the condition and the event has occurred, collect the second level of data from the at least one hardware device, and store the second level of data obtained from the at least one hardware device.

Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.

Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.

Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.

Abstract: A data storage device may include: a nonvolatile memory device including first and second memory regions configured to be read-interleaved with each other; and a processor configured to select a first read command among read commands received from a host device, select a second read command among the read commands excluding the first read command, and control the nonvolatile memory device to perform map read on the first and second read commands at the same time. The processor selects, as the second read command, at least one read command that is configured to be read-interleaved with the first read command.

Abstract: An apparatus includes an interface circuit and a monitor circuit communicatively coupled to the interface circuit. The monitor circuit is configured to identify a command issued to a memory communicatively coupled to the monitor circuit through the interface circuit, determine whether the command is authorized, and, based on a determination that the command is not authorized, cancel the command.

Abstract: An intelligent journal-aware caching manager for journaled data is provided. The caching manager ensures that data is not duplicated in a write-ahead-log (“journal”) and volatile cache memory (“cache”). The caching manager maintains first-in-first-out (“FIFO”) policy for the journal as needed and includes an alternate caching policy for non-journaled data.

Abstract: The embodiments set forth techniques for facilitating processing checkpoints between computing devices. A method can be performed by at least one first computing device configured to interface with a first server computing device cluster, and include (1) processing objects managed by the first server computing device cluster, where the objects are stored across at least two first partitions associated with the first server computing device cluster, (2) detecting a condition to facilitate a processing checkpoint with at least one second computing device configured to interface with a second server computing device cluster, where the objects are mirrored—but stored differently across at least two second partitions associated with the second server computing device cluster, (3) gathering, from each partition of the at least two first partitions, information associated with a particular number of last-processed objects, and (4) providing the information to the at least one second computing device.

Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; determining whether a first ratio of a first quantity of a first bit value and a second quantity of a second bit value in the first data is greater than a threshold; when the first ratio is not greater than the threshold, performing a decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold, not performing the decoding operation according to the first data.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. For example, the computing device monitors storage unit (SU)-based write transfer rates and SU-based write failure rates associated with each of the SUs for a write request of encoded data slices (EDSs) to the SUs within the DSN. The computing device generates and maintains a SU write performance distribution based on monitoring of the SU-based write transfer rates and the SU-based write failure rates and adaptively adjusts a trimmed write threshold number of EDSs and/or a target width of EDSs for write requests of sets of EDSs to the SUs within the DSN.

Abstract: A system for providing a virtual data storage medium according to an embodiment of the invention may be a system for providing a virtual data storage medium using data storage federation, where the system may include: heterogeneous data storage media including a multiple number of data storage media using different interfaces, protocols, and commands for using stored data; and a federation unit configured to generate a virtual data storage medium by federating the heterogeneous data storage media.

Abstract: A method and apparatus are described for assigning mastership of nodes to data blocks. A method involves connecting each session of a plurality of sessions to a particular node of a cluster of nodes based on services associated with the plurality of sessions. Each session of the plurality of sessions is associated with a respective service of a plurality of services. The method also involves collecting service-based access statistics aggregated by service and ranges of data block addresses. Each range corresponds to one or more contiguous subrange of data block addresses. The method further involves assigning mastership of the nodes to the data blocks having addresses within said ranges of data block addresses based on services associated with the nodes and the service-based access statistics.

Abstract: One example method includes creating a copy of a dataset, wherein the dataset is a backup that was previously created and stored. The copy of the dataset may be a clone, or a snapshot. The method further includes indexing a portion of the copy, mounting the copy at a proxy, associating the index with data in the copy, storing the index, and then using the index to search the copy. The search may be performed in response to a request from a user.

Abstract: Devices and systems for distributing data across disaggregated memory resources is disclosed and described. An acceleration controller device can include an adaptive data migration engine (ADME) configured to communicatively couple to a fabric interconnect, and is further configured to monitor application data performance metrics at the plurality of disaggregated memory pools for a plurality of applications executing on the plurality of compute resources, select a current application having a current application data performance metric, determine an alternate memory pool from the plurality of disaggregated memory pools estimated to increase application data performance relative to the current application data performance metric, and migrate the data from the current memory pool to the alternate memory pool.

Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.