Abstract: Techniques relating to fused objects are disclosed. Embodiments include verifying the validity of a transition from a current tail template to a new tail template for a fused object. The validity of the transition is determined by analyzing the type transitions per memory slot. If the type transition, for each memory slot, constitutes a type-compatible transition, then the transition from the current tail template to the new tail template is valid. If the type transition, for any memory slot, is not type-compatible, then the transition from the current tail template to the new tail template is not valid. Embodiments include generating a fused object with a repeating tail. A tail template associated with a fused object is repeated multiple times in the tail of the fused object.

Abstract: A disclosed example method to perform memory copy operations includes copying a first portion of data from a source location to a destination location, the first portion of the data being less than all of the data intended to be copied from the source location to the destination location; determining a cache miss measure indicative of an amount of the first portion of the data that is located in a cache; selecting a type of memory copy operation based on the cache miss measure; and initiating a memory copy operation based on the selected type of memory copy operation to copy a second portion of the data from the source location to the destination location.

Abstract: A memory arrangement having a memory, a first buffer memory, a first buffer memory controller which, during the storage of memory contents from the memory in the first buffer memory, is configured to invalidate the memory contents in the memory by means of a modification, a second buffer memory and a second buffer memory controller which is configured to read memory contents from the memory, to check whether the memory contents read from the memory are valid and, if the memory contents read from the memory are invalid, to apply a reversal of the modification to the read memory contents.

Abstract: An apparatus and method are provided for managing a cache hierarchy. The apparatus has processing circuitry for executing instructions, and a cache hierarchy for storing content for access by the processing circuitry when executing those instructions. The cache hierarchy has a plurality of levels of cache including a highest level of cache that is accessed prior to the other levels of cache in response to a request from the processing circuitry. Eviction control circuitry is provided in association with each level of cache, and the eviction control circuitry associated with a chosen level of cache in arranged to implement a most recently read eviction policy that causes content most recently read from the chosen level of cache to be selected for eviction from that chosen level of cache. It has been found that such an approach can significantly increase the effective cache capacity within the cache hierarchy, without the complexities often associated with other schemes.

Abstract: A system transmits a target data file as a set of mathematical functions and data values representative of the target data file to a receiver, the system comprising at least one hardware processor and memory storing computer instructions, the computer instructions when executed by the at least one hardware processor configured to cause the system to identify a target bit pattern of a target data file; generate a set of mathematical functions and data values operative to generate the target bit pattern; and transmit the set of mathematical functions and data values to a receiver, which can use the set of mathematical functions and data values to generate the target data file.

Abstract: A computing device with a multicore processing unit and a memory management unit (MMU) may provide multi-order failure resistant data isolation and segregation with a cross domain filtration system. The multicore processing unit may include a first processor, a second processor, and a third processor. A first processor may process data via an egress filter task(s). The MMU may allow the egress filter task(s) to write the data to a first segregated physical memory location. A second processor may perform filtering of the data via a cross domain filter task(s). The MMU may allow the cross domain filter task(s) to read from the first segregated physical memory location and write to a second segregated physical memory location. A third processor may process the data via an ingress filter task(s). The MMU may allow the ingress filter task(s) to read the data from the second segregated physical memory location.

Abstract: Initializing a data structure for use in predicting table of contents (TOC) pointer values. A request to load a module is obtained. Based on the loaded module, a pointer value for a reference data structure is determined. The pointer value is stored in a reference data structure tracking structure, and used to access a variable value for a variable of the module.

Abstract: Disclosed herein are various systems, methods, and processes for sharing a storage device with multiple virtual machines. A pseudo-identity is created for a storage device. Information in a hypervisor is configured to modify a response to a command issued to the storage device by a virtual machine. Physical characteristics of the storage device are determined and it is also determined whether the physical characteristics are acceptable. If the physical characteristics are acceptable, a virtual disk associated with the virtual machine is used. If the physical characteristics are unacceptable, a mapping of the virtual machine is migrated to another storage device.

Abstract: A machine-implemented method for managing a flash storage system includes determining a projected life value for each of a plurality of flash memory devices in the flash storage system, wherein the projected life value for at least one of the plurality of flash memory devices is higher than the projected life value of at least another one of the plurality of flash memory devices. The method also includes determining operating parameters for each of the plurality of flash memory devices based on the respective projected life values for the plurality of flash memory devices. The method also includes configuring the plurality of flash memory devices based on the determined operating parameters.

Abstract: A Data Storage Device (DSD) includes at least one non-volatile storage media. A command is received to modify a portion of a data object or file, with the command being byte-addressable for overwriting, deleting or adding the modified portion. The modified portion of the data object or file is written with an indication of a page container entry at a storage location in the at least one non-volatile storage media. The page container points to a previous storage location for previously written data for the data object or file that was most recently written before writing the modified portion. A mapping or data container entry in a container data structure is updated for the data object or file to point to the storage location storing the modified portion of the data object or file and the indication of the page container entry.

Abstract: A memory system connected to a processor is described. The memory system includes a volatile first storage section, a nonvolatile second storage section having a smaller storage capacity than that of the first storage section, and a storage control section that performs control to store data sets in the second storage section. Each of the data sets including data written in the first storage section in response to a write command from the processor, address information indicating a write destination in the first storage section, and address information indicating a write destination in a nonvolatile third storage section to which the data written in the first storage section is to be written back.

Abstract: The present disclosure discloses a data push method and device, a storage medium, and an electronic device. The method includes: acquiring to-be-pushed data and identifier information of the to-be-pushed data, the identifier information of the to-be-pushed data uniquely identifies the to-be-pushed data; and pushing the to-be-pushed data if indication information is not stored at a target storage location in a storage space, the target storage location comprising a storage location corresponding to the identifier information of the to-be-pushed data, and the indication information indicating identifier information of data that had been pushed.

Abstract: In one embodiment, an apparatus includes a memory access circuit to receive memory access instructions and provide at least some of the memory access instructions to a memory subsystem for execution. The memory access circuit may have a conversion circuit to convert the first memory access instruction to a first subline memory access instruction, e.g., based at least in part on an access history for a first memory access instruction. Other embodiments are described and claimed.

Abstract: Systems and methods for managing content in a flash memory and to managing a lifespan of the flash memory. The lifespan is managed by throttling writes when usage exceeds certain quotas. The throttling may be performed in a cooperative manner such that the clients writing to the flash memory can implement their own throttling. The quotas are not rigid and allow flexibility to certain situations. When excessive quota is used, future quotas can be managed to bring the overall usage into an expected range.

Abstract: A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.

Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).

Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

Abstract: A qualifying system receives a channel activity record from one of a plurality of different external systems, over one of a plurality of different communication channels. It accesses qualification rules to determine whether the channel activity record is to be transformed into one or more target entities in a computing system. If so, a conversion engine accesses user-configurable mappings and conversion rules to identify conversion actions that are to be taken in order to transform the channel activity record into one or more target entities. The conversion engine performs a data transformation on the channel activity record to transform it into the identified one or more target entities.

Abstract: Multiple partitions can be run on a computing device, each partition running multiple processes referred to as a workload. Each of the multiple partitions, is isolated from one another, preventing the processes in each partition from interfering with the operation of the processes in the other partitions. Using the techniques discussed herein, some memory pages of a partition (referred to as a sharing partition) can be shared with one or more other partitions. The pages that are shared are file backed (e.g., image or data files) or pagefile backed memory pages. The sharing partition can be, for example, a separate partition that is dedicated to sharing memory pages.