Abstract: A current steering comparator includes an amplifier circuit, a bias circuit, a latch circuit, and a detector circuit. The amplifier circuit is configured to compare a first input signal with a second input signal during a comparison phase, in order to output a first signal and a second signal. The bias circuit is configured to utilize a tunable capacitor to bias the amplifier circuit during the comparison phase. The latch circuit is configured to generate a first output signal and a second output signal according to the first signal and the second signal during the comparison phase. The detector circuit is configured to detect the first output signal and the second output signal according to a predetermined clock signal to generate a control signal, in order to adjust the tunable capacitor.

Abstract: An integrated circuit for hardware security comprises a voltage glitch detection processing system comprising an oscillator circuit that generates and outputs a local oscillator clock which is a function of a supply voltage; a counter clocked by the oscillator circuit to generate at least one count value; and a capture section that synchronizes the at least one count value into a system clock domain for detecting a voltage glitch in the supply voltage.

Abstract: A wireless power system has a wireless power transmitting device such as a charging puck and a wireless power receiving device such as a battery-operated device. The charging puck may be connected to a plug via a cable. The plug may include a boot and a connector. The boot may house a printed circuit board that is positioned closer to one of the boot housing walls.

Abstract: A comparator circuit includes: a comparator comprising: a first input terminal receiving an input voltage; a second input terminal receiving a reference voltage; an output terminal outputting an output signal according to a result of a comparison between the input voltage and the reference voltage; and a power supply terminal receiving an operating voltage; and a mode controller applying a first operating voltage and a first reference voltage to the second input terminal and the power supply terminal of the comparator for a predetermined delay time in response to a supply of power being initiated from a power supply, and applying a second operating voltage and a second reference voltage to the second input terminal and the power supply terminal of the comparator in response to the delay time elapsing, wherein the first operating voltage is higher than a ground voltage and is lower than the second operating voltage.

Abstract: A power supply semiconductor integrated circuit includes an output transistor, a control circuit, a first-fault detection circuit, a second-fault detection circuit, a delay circuit, and a latch circuit. The output transistor is connected between a voltage-input terminal to which a DC voltage is input and a voltage-output terminal. The control circuit controls the output transistor. The first-fault detection circuit detects a first fault. The second-fault detection circuit detects a second fault different from the first fault. The delay circuit delays an output of the first-fault detection circuit and an output of the second-fault detection circuit. The latch circuit captures and holds an output of the delay circuit. The delay circuit includes: a constant current source for charging a delay capacitor; a discharge switch for discharging the delay capacitor; and a voltage comparator circuit that compares a charge voltage across the delay capacitor and a predetermined voltage.

Abstract: Exemplary embodiments may include a method of applying a charging pulse to an output capacitor, detecting satisfaction of a charging threshold, ending the charging pulse in response to the detecting the satisfaction of the charging threshold, and discharging the sampling capacitor in response to the detecting the satisfaction of the charging threshold. In some embodiments, once a sampling capacitor voltage drops below a discharging threshold, a charging pulse is applied. Exemplary embodiments may also include an apparatus with a controller coupled to an input node, a timer coupled to the controller, an inductive charger coupled to the controller, to an input node, and to an output node, and a sensor coupled to the controller and the output node. Exemplary embodiments may further include an apparatus where a sensor with a sampling capacitor has a first terminal coupled to the output node and a second terminal coupled to the controller and the inductive charger.

Abstract: A small size, energy harvesting, long distance wireless AC sensor module. The sensor module includes an electromagnetic energy harvesting method that supplies and manages power to the sensor. Therefore, the sensor module does not rely on wired power or battery to run. The sensor also includes a low power wireless transmitter that has transmission frequency of sub-1 GHz and effective transfer distance of more than 100 meters, more than 150 meters, more than 200 meters and up to 250 meters. It has small size preferably having a size of less than 68 mm long by 33 mm wide by 21 mm thick, less than 50 grams. Thanks to the wireless and energy harvesting features, the sensor is very easy to install. Users just need to clamp sensors to the subject electrical lines, and then the data will be sent to data gateways automatically.

Abstract: A comparator includes an input stage having a differential input and an output, wherein the voltage at the output is in response to the voltage at the input. The comparator further includes a current limiter for limiting the current flow through the input stage, wherein the current flow through the input stage is in response to the voltage at the input.

Abstract: This invention provides a resistance-adjustable means using at a pull-up driver and/or a pull-down driver of an OCD circuit. When the resistance-adjustable means is applicable to the pull-up driver, the resistance-adjustable means includes a triode-mode PMOS coupled to a circuit of the pull-up driver and at least one of one or more adjustable resistors and/or a fixed resistor, which are connected in series and coupled to the triode-mode PMOS, and the at least one of the adjustable resistors or the fixed resistor is coupled to an IO (input/output) pad. When the resistance-adjustable means is applicable to the pull-down driver, a triode-mode NMOS is used to replace the triode-mode PMOS for the resistance-adjustable means.

Abstract: According to one aspect of the present disclosed subject matter, a receiver inductively powered by a transmitter for powering a load, the receiver comprising: a resonance circuit capable of tuning its resonance frequency for coupling with the transmitter and generate AC voltage; a power supply section configured to rectify the AC voltage and adjust a DC current and a DC voltage to the load; and a control and communication section designed to set parameters for the receiver and communicate operation points (OP) to the transmitter, wherein the parameters and the OP derived from determining a minimal power loss of the receiver.

Abstract: A comparator includes: a first stage circuit, configured to receive a voltage signal to be compared and a reference voltage signal Vref, and to generate and output a first amplifying signal and a second amplifying signal based on the voltage signal to be compared and the reference voltage signal Vref; a second stage circuit, connected with the first stage circuit, configured to generate and latch a first output signal and a second output signal based on the first amplifying signal and the second amplifying signal; wherein the first stage circuit and/or the second stage circuit include(s) a first pair of cross-coupled transistors.

Abstract: The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a variable impedance module with a first capacitor coupled to a first input terminal and the second capacitor coupled to a second input terminal. A diode bridge is connected between the input capacitors. The anodes of the top diodes are connected to a supply through a resistor, and the cathodes of the lower diodes are connected to a high-impedance current source. A third capacitor is connected between these two nodes.

Abstract: Circuits, systems, and methods are described herein for generating master clock signals and slave clock signals for controlling a flip-flop having a master latch and a slave latch. A circuit includes a master latch configured to latch an input data signal and to output a data latch signal based on a master clock signal. The circuit also includes a slave latch coupled to the master latch and configured to generate an output data signal based on a slave latch clock signal and the data latch signal. Additionally, the circuit includes a skewed clock circuit coupled to the master latch and the slave latch. The skewed clock circuit is configured to receive a clock signal and generate the master clock signal and the slave clock signal based on the clock signal. The master clock signal and the slave clock signal are independent clock signals whose timing is skewed relative to one another by the skewed clock circuit.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: A power control circuit comprising a power supply and a load, the load being synthesized from an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped in impedance modules. The impedance elements in each impedance module are of equal value, while those between the modules bear ratios uniquely defined according to the numbers of impedance elements in the impedance modules. A number of switches associated with said impedance elements short out a selected number of the impedance elements under the control of a first analog signal which may be preprocessed by an analytic function. The analog signal is converted to digital signals by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, whereby the amount of power delivered to the load is controllable by the first analog signal.

Abstract: A power delivery system may include a first voltage regulator configured to output an upper intermediate voltage about an expected discharge voltage plateau of a battery for use by the power delivery system, a switched capacitive charge pump configured to down convert the upper intermediate voltage of the first voltage regulator to a lower intermediate voltage, and a second voltage regulator configured to use the lower intermediate voltage to provide power to a load.

Abstract: The present invention relates to an electronic device including an input and an output, the device generating an output voltage when the input of the device is supplied, the device comprising: a conversion unit converting a spin current into a charge current having an amplitude and a sign, a spin current application unit applying a spin current to the conversion unit, a ferroelectric layer, which has a ferroelectric polarization and is arranged such that the ferroelectric polarization controls at least one among the amplitude and the sign of the charge current, and an electric field application unit suitable for applying an electric field to the ferroelectric layer to control the ferroelectric polarization.

Abstract: Provided is a receiver. The receiver according to the inventive concept includes a first filter circuit, a second filter circuit, and an amplifier. The first filter circuit provides a first path for first frequency components below first cutoff frequency of input frequency components and passes second frequency components except for the first frequency components of the input frequency components through second path. The second filter circuit attenuates third frequency components below a second cutoff frequency of the second frequency components. The amplifier amplifies the second frequency components including the attenuated third frequency components.

Abstract: A memory system in an embodiment includes; one or more memory chips; and a controller connected to the one or more memory chips, the controller including a first driver configured to send a sending signal to the one or more memory chips, a second driver configured to generate a boost signal that is added to the sending signal, and a control circuit configured to set an addition period for the boost signal based on information relevant to a characteristic of distortion that occurs in the sending signal to the one or more memory chips.

Abstract: Various embodiments include a device for coupling two DC grids comprising source-side and load-side capacitances comprising: a switching device for current regulation, the switching device including two series-connected switching modules; wherein each of the switching modules includes at least one controllable semiconductor switching element connected in parallel to a respective series circuit comprising a resistor and a capacitor; and a control unit.