Abstract: Systems and methods for detecting an open condition in a master-slave configuration are described. In an example, a controller can be integrated in a slave device of a master-slave configuration. The controller can be configured to activate a current source to supply a current to a pin of the slave device. The controller can be further configured to compare a voltage measured at the pin of the slave device with a reference voltage. The controller can be further configured to, based on the comparison, determine a presence or an absence of an open condition associated with the pin of the slave device. The controller can be further configured to output a signal representing the determination of the presence or the absence of the open condition to a master device.

Abstract: The present invention discloses a voltage level conversion circuit. A first and a second N-type driving transistors turn on when a first power voltage source supplies a high state voltage. A voltage transmission circuit transmits a first and a second input voltages having opposite levels to sources of the first and the second N-type driving transistors. A current source operates according to a second supply voltage source and has a first and a second output terminals. A first and a second connection transistors respectively couple between the drain of the first N-type driving transistor and the second output terminal and between the drain of the second N-type driving transistor and the first output terminal. The first and the second connection transistors turn on and off when the first voltage supply source supplies the high state voltage and a low state voltage.

Abstract: Disclosed are circuits and methods for a comparator with a floating capacitive supply. A capacitor is coupled between a comparator and a power supply. Two sets of electronic switches are configured in opposing operational states to shift the configuration of the circuit between a charging configuration and a decision configuration. In the charging configuration, the capacitor draws current from the power supply. In the decision configuration, the comparator pulls current from the capacitor to perform a decision. The configuration of the two sets of switches is alternated to toggle between the charging configuration and the decision configuration, allowing for the capacitor to be recharged between each decision performed by the comparator.

Abstract: A power converter circuit included in a computer system includes a switched-capacitor circuit as well as one or more bypass devices, and generates a particular voltage on a regulated power supply node. In response to situations that can result in a rapid transient of the voltage level on the regulated power supply node (e.g., upscaling or downscaling), the power converter circuit may activate the bypass devices to source or sink current from the regulated power supply node. By employing both the switched-capacitor circuit and the bypass devices, the power converter may be able to more rapidly adjust the voltage level of the regulated output supply node, as well as maintain voltage across the devices and capacitors included in the switched-capacitor circuit within specified tolerances.

Abstract: A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.

Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.

Abstract: A power source switching device that includes: a switch connected to a signal input terminal via a first resistor element and configured to fix a potential of the signal input terminal at a predetermined potential by adopting an ON state in a case in which a selection signal is not input; and a switch control circuit configured to perform control to place the switch in an OFF state based on a state signal indicating an operational state of a circuit that operates when supplied with power from a power source selected according to the selection signal in a case in which a potential of the selection signal is different from the predetermined potential, and to perform control to place the switch in the ON state in a case in which the selection signal is not input.

Abstract: According to one embodiment, an electronic apparatus includes a control circuitry and a transmitter. The control circuitry is configured to select a first frequency band based on channel information on at least one communication channel included in a communication frequency band of a wireless communication standard. The transmitter transmits power via an electromagnetic wave in the first frequency band.

Abstract: A level shifter includes a self-initialization circuit. The self-initialization circuit judges whether the input signal and the inverted input signal received by the level shifter are invalid while a power supply voltage is powered up. If the self-initialization circuit confirms that the input signal and the inverted input signal received by the level shifter are invalid, the self-initialization circuit controls the level shifter to be maintained in a self-initializing power up state. Consequently, the output signal from the level shifter has the specified voltage level.

Abstract: Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.

Abstract: A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.

Abstract: An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

Abstract: An integrated circuit includes a first input port configured to receive a supply voltage from a switched-mode power supply (SMPS), where frequency components of the supply voltage include harmonics of a reference frequency, where the reference frequency is equal to a first frequency divided by a factor; and a spurious components cancellation circuit coupled to the first input port, where the spurious components cancellation circuit is configured to: generate a first clock signal having the reference frequency; adjust an amplitude and a phase of the first clock signal to form a compensation signal; and add the compensation signal to the supply voltage to produce a modified supply voltage with reduced frequency components at one or more harmonic frequencies of the reference frequency.

Abstract: An energy efficiency control method and apparatus are provided. The method, implemented by a communications device comprising a primary power supply, a secondary power supply, and a control apparatus, includes: obtaining a current load rate of the primary power supply and a load power of the secondary power supply; determining, based on the obtained current load rate and the load power, a target output voltage of the primary power supply and a target input voltage of the secondary power supply that satisfy an energy efficiency requirement of the communications device, wherein energy efficiency of the communications device is related to the energy efficiency of the primary power supply and the energy efficiency of the secondary power supply; and controlling the primary power supply to output the target output voltage, and controlling an input voltage of the secondary power supply to be the target input voltage.

Abstract: Provided is a current generation circuit including a first terminal to be connected to a first external circuit; a second terminal to be connected to a second external circuit; a first resistor in which a potential is generated by the first external circuit connected through the first terminal; a second resistor in which a potential is generated by the second external circuit connected through the second terminal; a first amplifier circuit including a first positive input terminal to which the potential generated in the first resistor is supplied, and a first negative input terminal to which the potential generated in the second resistor is supplied; and a first MOS transistor having a gate connected to an output terminal of the first amplifier circuit, a source connected to the first negative input terminal, and a drain connected to a first differential current terminal.

Abstract: A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.

Abstract: Disclosed is a system for tracking a maximum power point. The system includes an energy harvesting device, a power management integrated circuit including a switching circuit that adjusts an input voltage that is transmitted from the energy harvesting device and a conversion circuit that converts the input voltage adjusted by the switching circuit to output an output voltage, and a measuring device that calculates a ratio of a second power based on the input voltage to a first power based on an open circuit voltage of the energy harvesting device, using an internal impedance of the energy harvesting device and an input impedance of the power management integrated circuit.

Abstract: A system includes a power regulator coupled between a coil and a battery, wherein the power regulator is configured as a linear regulator when power is provided from the coil to the battery, and a current sense apparatus having two inputs coupled to an input and an output of the power regulator, respectively, wherein the current sense apparatus is configured to sense a bidirectional current flowing through the power regulator.

Abstract: A wireless power transfer system includes: (a) an annular first substrate, a first coil, a second coil, and an annular second substrate that are stacked such that central axes of those substantially coincide with each other; (b) a power transmission circuit, implemented on the first substrate, for applying a voltage to the first coil; and (c) a power reception circuit, implemented on the second substrate, for rectifying an electric current that is generated at the second coil through electromagnetic induction and/or magnetic resonance. The second substrate is a multilayer substrate that includes a first layer provided with a ground pattern and a second layer provided with a power supply pattern, and includes slit portions where the patterns are not present as viewed from a direction of the central axes.

Abstract: Provided herewith is a closed loop circuit including a transistor operable as a microscopic switch device to amplify electron pressures. The transistor has a collector connected to a positive voltage source. An optocoupler is provided, connected in parallel to the positive voltage source, and triggered in response to a triggering unipolar pulse from a network. An output of the optocoupler is connected to a base of the transistor. A capacitor is provided, connected between the emitter of the transistor and a ground, and having an anode and a cathode for receiving a capacitive dielectric medium therebetween, such that, electrons flow through dielectric medium to the transistor from a ground state in order to break down the dielectric material. In the preferred embodiment, the dielectric material includes water which is dissociated into hydrogen and oxygen.