Abstract: The present invention provides a reference voltage buffer comprises a reference voltage generator, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors and a second load. In the reference voltage buffer, the first load and the second load use active device to increase the settling time, and the first load, the second load and the reference voltage generator of the reference voltage buffer are resigned to have the same characteristics in response to the temperature variation to overcome the PVT issue, and the first load and the second load of the reference voltage buffer use the open-loop design to have large full-scale of the output reference voltages.

Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.

Abstract: A voltage converting device includes: a DC/DC converter configured to step down a voltage of a power supply and output the stepped-down voltage to a low-voltage power supply having a voltage lower than a voltage of the power supply; a control device configured to control the DC/DC converter; and a determining unit configured to determine whether a voltage of the power supply input to the DC/DC converter is within a predetermined voltage range, wherein the control device switches, on the basis of a determination result of the determining unit, between a first control in which the DC/DC converter is caused to perform a step-down operation and electric power is supplied to a load connected to the low-voltage power supply and a second control in which a step-down operation of the DC/DC converter stops and electric power is supplied from the low-voltage power supply to the load.

Abstract: An offset corrected bandgap reference and temperature sensor is disclosed. In a complementary metal-oxide-semiconductor (CMOS) bandgap reference, non-idealities in the operational amplifier (op-amp) bandgap reference circuit can lead to a voltage offset. This operational amplifier offset voltage is the dominant source of error in the bandgap reference. If the bandgap reference is used in a temperature sensor, it only needs to be accurate during the analog-to-digital conversion cycle. Embodiments of the present disclosure employ switched capacitors to store the operational amplifier offset during a sample mode in which the bandgap reference operates continuous-time. The operational amplifier offset is then corrected during a hold mode while the temperature sensor completes the analog-to-digital conversion.

Abstract: An operational amplifier includes a first output transistor and a second output transistor connected in series between two power nodes, the second output transistor having a semiconductor type opposite to the first output transistor, the first output transistor and the second output transistor being electrically coupled at an output node, and gates of the first output transistor and the second output transistor being connected to a first drive node and a second drive node respectively; and a decoupling capacitor circuit electrically connected between the first drive node and the second drive node.

Abstract: Provided is a wireless power transmission system for a rotating connector. A wireless power transmission system for a rotating connector according to an embodiment of the present invention comprises: a wireless power transmission module comprising a first magnetic core and a first coil, provided on a fixed first connector, and using the power thereof to generate a magnetic field and transmit wireless power; and a wireless power receiving module comprising a second magnetic core and a second coil, and provided on a second connector, which is rotatably connected to the first connector, to receive the transmitted wireless power and supply same to the second connector. The first and second magnetic cores are positioned in a straight line along the rotational axis of the second connector.

Abstract: According to one aspect of the present disclosed subject matter, a receiver inductively powered by a transmitter for powering a load, the receiver comprising: a resonance circuit capable of tuning its resonance frequency for coupling with the transmitter and generate AC voltage; a power supply section configured to rectify the AC voltage and adjust a DC current and a DC voltage to the load; and a control and communication section designed to set parameters for the receiver and communicate operation points (OP) to the transmitter, wherein the parameters and the OP derived from determining a minimal power loss of the receiver.

Abstract: A clock synchronization signal generator generates a dead time in which gates of both of two switching elements included in a switching circuit are in an off state, and generates the dead time for controlling a plurality of pulses having different widths to pulses having a constant width, which is output by the switching circuit.

Abstract: Subject matter disclosed herein may relate to correlated electron switches.

Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes.

Abstract: The present disclosure aims to reduce the changes that a control unit receiving power supplied from a power supply cannot perform control of a precharge operation even if the power supply voltage drops. In a power supply device, a reverse-flow prevention switching element is configured such that a plurality of semiconductor switching elements are connected in parallel with each other. The control unit, in accordance with a predetermined precharge condition being fulfilled, causes the second voltage conversion unit to perform the second voltage conversion operation by supplying a second control signal for switching to an ON signal and an OFF signal alternately to only some of the plurality of semiconductor switching elements constituting the reverse-flow prevention switching element.

Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.

Abstract: A wireless power transmitter according to various embodiments comprises: a power transmission antenna array capable of transmitting power in a wireless manner; a driving circuit for mechanically adjusting the steering direction of the power transmission antenna array; and a processor, wherein the processor can be configured so as to determine the direction in which an electronic device is positioned, control the driving circuit such that the driving circuit mechanically adjusts the steering direction of the power transmission antenna array when the direction in which the electronic device is positioned is not included in a coverage corresponding to the steering direction of the power transmission antenna array, and control the power transmission antenna array such that the power transmission antenna array transmits the power to the electronic device.

Abstract: A control device may be configured to control an amount of power delivered to one or more electrical loads and provide various feedback associated with the control device and/or the electrical loads. The control device may be a wall-mounted device or a battery-powered remote control device. The feedback may indicate the amount of power delivered to the one or more electrical loads. The feedback may also indicate a low battery condition. The control device may include a light bar and/or one or more indicator lights for providing the feedback.

Abstract: A data demodulating circuit includes a sensing circuit sensing a power signal applied to a coil at first and second times, and outputting an analog value representing a difference in voltage of the power signal at the first and second times. An analog-to-digital converter digitizes the analog value output by the analog voltage differential sensing circuit to produce a digital code. A compensation circuit, over a period of time, compares a present value of the digital code to a first value of the digital code during the period, and subtracts a given value from the present value of the digital code if the present value is greater than the first value but add the given value to the present value of the digital code if the present value is less than the first value. An accumulator accumulates output of the compensation circuit, and a filter filters output of the accumulator.

Abstract: An example of an apparatus includes a bias circuit having first and second bias circuit outputs. The apparatus also includes a comparator having first and second comparator inputs. The apparatus also includes a first capacitor coupled between the second comparator input and the second bias circuit output. The apparatus also includes a first switch coupled between the second comparator input and the second bias circuit output. The apparatus also includes a second switch coupled between the first bias circuit output and an input terminal, a third switch coupled between the input terminal and the first comparator input, and a fourth switch coupled between the first bias circuit output and the first comparator input. The apparatus also includes a second capacitor coupled between the first comparator input and the second bias circuit output.

Abstract: Startup charge balancing circuits and methods for capacitive charge pumps that avoid large in-rush currents and resulting voltage spikes. Embodiments include a charge balance circuit coupled to a corresponding charge pump capacitor of a charge pump. The charge balance circuit includes a comparator that compares the output voltage of the charge pump to a feedback voltage derived from the voltage across the corresponding charge pump capacitor. In response, either a constant current source or a constant current sink is coupled to the charge pump capacitor. Current sourcing or sinking continues until the voltage across the corresponding charge pump capacitor approximates a target voltage, at which point the comparator output toggles, which results in uncoupling of the coupled current source or current sink from the corresponding charge pump capacitor. Embodiments only need one current sink and one current source per charge pump capacitor, and charge balancing is independent of leakage currents.

Abstract: According to an embodiment, there is provided an energy harvesting system using linear kinetic energy based on induction power generation. According to various embodiments, there may be provided an energy harvesting system using linear kinetic energy based on induction power generation, which may minimize the occasions of replacing or recharging the battery in battery-powered products by using the force or energy generated from a linearly reciprocating machine or device and may allow the battery to be charged when linear kinetic energy is generated and, otherwise, discharged, using an automatic battery charging/discharging system.

Abstract: A device for harvesting electrical energy includes a rectifier and a control device. The rectifier includes a first charging circuit for harvesting energy from a positive voltage of an energy harvester, and a second charging circuit for harvesting energy from a negative voltage of the energy harvester. The charging circuits include a common coil and a common electronic switch. Furthermore, each of the charging circuits includes a capacitor and a blocking element. Because the charging circuits use the coil jointly, the device is designed in a simple and compact manner. In addition, the energy harvesting is efficient, due to the one-stage AC-DC conversion and due to a maximum power point tracking function of the control device.

Abstract: A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.