Abstract: A memory device includes a first strobe delay circuit delaying a first data strobe signal to generate a delayed first data strobe signal, a first write leveling circuit sampling a first delay clock in synchronization with the delayed first data strobe signal, a second strobe delay circuit delaying a second data strobe signal to generate a delayed second data strobe signal, a replica second strobe delay circuit delaying the first data strobe signal by a delay value obtained by replicating the second strobe delay circuit to generate a replica delayed second data strobe signal; and a second write leveling circuit sampling a second delay clock in synchronization with the delayed second data strobe signal in a first I/O mode, and sampling the second delay clock in synchronization with the replica delayed second data strobe signal in a second I/O mode.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Abstract: In a method of reading a resistive memory device according to an embodiment, a memory cell including a selection element and a variable resistance element is prepared. The selection element exhibits a snap-back behavior on a current-voltage sweep curve for the memory cell. First and second read voltages to be applied to the memory cell are determined within a voltage range in which the selection element maintains a turned-on state. The magnitude of the second read voltage is less than that of the first read voltage and selected in a voltage range in which the selection element exhibits the snap-back behavior. The first read voltage is applied to the memory cell to measure a first cell current. The second read voltage is applied to the memory cell to measure a second cell current. A resistance state stored in the memory cell is determined based on the first cell current and the second cell current.

Abstract: The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.

Abstract: A memory device and a data refreshing method thereof are provided. When an automatic refresh word line address and a row hammer refresh word line address belong to the same memory cell array, memory cells corresponding to the automatic refresh word line address are refreshed, and a time to refresh memory cells corresponding to the row hammer refresh word line address is postponed.

Abstract: A method of operating a semiconductor memory device including a memory cell array and an error correction circuit is provided as follows. A write command, main data and an address are received from a memory controller. An error correction data unit is provided to the error correction circuit. The error correction data unit includes the main data. At least one parity bit is generated based on the error correction data unit. A write operation is performed, in response to the write command, on a target page selected by the address so that the at least one parity bit and the main data are written to the target page and the at least one parity data is written later than the main data to the target page.

Abstract: A bit line power supply apparatus including a bit line high voltage generator is provided. The bit line high voltage generator includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit includes a first sensor and a first linear voltage regulator. The first sensor compares a first reference voltage with a bit line high voltage to generate a first sensing voltage according to a first control signal. The first linear regulator generates the bit line high voltage according the first sensing voltage. The second voltage generation circuit includes a second sensor and a switching voltage regulator. The second sensor compares the first reference voltage with the bit line high voltage to generate a second sensing voltage according to a second control signal. The switching regulator generates the bit line high voltage according the second sensing voltage.

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

Abstract: Systems and methods are described for predicting potential failures in flash memory devices by probing for memory cells with marginal programming characteristics. A method includes receiving a write request. The method also includes applying a predetermined number of programming pulses to a plurality of memory cells within a block of a flash memory device. The method also includes applying a verify pulse to each respective one of the plurality of memory cells. The method also includes storing programming status of the plurality of memory cells into a set of latches. The method also includes determining, based on the stored programming status, a total number of memory cells within the block that fall outside of one or more predetermined expected ranges. The method also includes identifying the block as a block in risk when the total number of memory cells satisfies a predetermined risk threshold.

Abstract: A nonvolatile memory includes a plurality of memory blocks, a plurality of source drivers corresponding to the plurality of memory blocks, a plurality of pass transistor groups connected between the plurality of source drivers and the plurality of memory blocks, a plurality of block pass transistors connected between a plurality of block word lines and the plurality of pass transistor groups, a plurality of block decoders corresponding to a plurality of memory block groups respectively, and a block pass transistor decoder configured to control voltages of block select lines connected to the plurality of block pass transistors. The plurality of memory blocks are divided into the plurality of memory block groups. Each block decoder is configured to control voltages of block word lines, among the plurality of block word lines, connected to at least two memory blocks of a corresponding memory block group in common.

Abstract: A solid state drive (SSD) device includes a first nonvolatile memory package, a second nonvolatile memory package, and a controller. The first nonvolatile memory package includes a first buffer chip and a plurality of first nonvolatile memory chips. The second nonvolatile memory package includes a plurality of second nonvolatile memory chips. The controller controls the first nonvolatile memory package and the second nonvolatile memory package. The first buffer chip communicates a first address signal and a first data with the controller, and selectively communicates the first data with one of the plurality of first nonvolatile memory chips and the plurality of second nonvolatile memory chips based on the first address signal.

Abstract: The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells and a second memory array comprising a second plurality of memory cells. Each memory cell of the first and second plurality of magnetic memory cells includes a magnetic memory element and a two-terminal selector coupled in series. The memory array structure further includes a first multiplexer coupled to a third plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a fourth plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and one or more latches coupled to the sense amplifier.

Abstract: A double data rate memory includes a circuit board, a goldfinger connection interface, at least 16 first IC chips, at least 16 second IC chips, a first and a second read-only memory. The circuit board has a first surface, a second surface, a first region and a second region. The first IC chips are disposed on the first surface. The second IC chips are disposed on the second surface. The first read-only memory is connected with the first and the second IC chips disposed on the first region. The second read-only memory is connected with the first and the second IC chips disposed on the second region. 10 pins of the goldfinger connection interface are connected with the second read-only memory and the first and the second IC chips disposed on the second region to make them operate. At least 32 IC chips are effectively operated in single one memory.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Abstract: An electronic device including a semiconductor memory may be provided. The semiconductor memory may include a write circuit configured for generating a first current. The semiconductor memory may include a first selection circuit configured for coupling the first write circuit to a first line based on a first selection signal. The semiconductor memory may include a second write circuit configured for generating a second current. The semiconductor memory may include a second selection circuit configured for coupling the second write circuit to a second line based on a second selection signal. The semiconductor memory may include a memory cell coupled between the first line and the second line. The semiconductor memory may include a voltage control circuit configured for controlling a voltage level of the second line.

Abstract: An EPROM device may include a unit cell, a switching unit, a multiplexer, and a comparator. The unit cell may be disposed between a bit line, which is coupled to a program voltage supply line, and a ground voltage terminal. The switching unit may be disposed between the bit line and the program voltage supply line, and may control an electrical coupling between the program voltage supply line and the unit cell according to a switching control signal. The multiplexer may selectively output a first reference voltage, a second reference voltage, and a third reference voltage according to an input of binary data. The comparator may compare an output signal of the multiplexer and the bit line, and generate the switching control signal.

Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a sensing circuit coupled between a sensing input line coupled to a bit line of the nonvolatile memory cell and a sensing output line, a sensing output grounding portion fixing an output signal of the sensing circuit at a low level if the output signal of the sensing circuit has a low level, and a bit line grounding portion fixing a bit line voltage at a ground voltage if the output signal of the sensing circuit is fixed at a low level.