Abstract: A magnetic storage apparatus is disclosed, and is configured to access data. The magnetic storage apparatus includes a magnetic storage track, a first write apparatus, a second write apparatus, and a drive apparatus. The first write apparatus and the second write apparatus are located at different positions on the magnetic storage track. The first write apparatus is configured to write first data “0” or second data “1”. The second write apparatus is configured to write third data “2” and fourth data “3”.

Abstract: According to one embodiment, a memory device includes a memory cell array; a generation circuit generating a reference current; a sense amplifier comparing a cell current flowing through a memory cell with the reference current; a first clamp transistor connected between the sense amplifier and the memory cell; a second clamp transistor connected between the sense amplifier and the generation circuit; a first interconnect layer connected to a gate of the first clamp transistor; a second interconnect layer connected to a gate of the second clamp transistor and arranged adjacent to the first interconnect layer; and a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer, a fixed voltage being applied to the first shield line.

Abstract: In one embodiment, an associative memory is built using multiple cascaded associative memory blocks, with stored lookup words spanning a same or different numbers of associative memory blocks. A first lookup operation is performed by a first associative memory to generate first matching indications of associative entries of the first associative memory that match both the first lookup word and the first lookup type. A second lookup operation is performed by an end associative memory to generate end matching indications of associative entries of the end associative memory that match both the end lookup word and the end of word lookup type. A final lookup result indicating a matching multi-block spanning associative memory entry based on the first matching indications and the end matching indications is determined and signaled by the associative memory is built using multiple cascaded associative memory blocks.

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

Abstract: A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information. The controller generates a voltage control signal in response to the boot-up enable signal. The fuse latch array stores repair information provided from the fuse block. The voltage control signal, which is used as a bulk bias of a transistor formed in the fuse latch array, is adjustable.

Abstract: A memory element according to an embodiment includes: first through fourth impurity layers arranged in a semiconductor layer including first to third portions; a first gate wiring line disposed on the first portion located between the first and second impurity layers; a second gate wiring line disposed on the second portion located between the second and third impurity layers; a third gate wiring line disposed on the third portion located between the third and fourth impurity layers; a first insulating layer disposed between the first portion and the first gate wiring line; a second insulating layer disposed between the second portion and the second gate wiring line; a third insulating layer disposed between the third portion and the third gate wiring line; first wiring line electrically connected to the first through third gate wiring lines; and second wiring line electrically connected to the first through fourth impurity layers.

Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Abstract: A memory controller according to an example embodiment of the present disclosure may include a duty ratio adjusting circuit which generates adjusted clock signals in response to a clock signal for strobing data, and a selection circuit which outputs one of the clock signal and the adjusted clock signals to a memory device as an output clock signal. Each of the adjusted clock signals may have a different duty ratio.

Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and in regard to the insulating layer and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film.

Abstract: A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows in each of the banks; and an address latch circuit configured to latch a full address specifying one of the word lines, the full address including a first address and a second address. The address latch circuit receives a first command and a second command to latch the first address and the second address in accordance with the first command and the second command, respectively. Paths for the first address and the second address are configured to be separate from each other.

Abstract: A table of error counts is generated based on reading wordlines of a flash memory device, the table storing an error count for each combination of wordline and respective read level voltage used to read the wordlines. A plurality of offset wordline groups are generated based on the table of error counts, with each group associating a different read level offset voltage with a plurality of wordline addresses. A storage device is configured to read memory cells using a read level offset voltage of a generated offset wordline group associated with a wordline address of the memory cells to be read. After a predetermined point in a life cycle of a respective memory block, the table is regenerated and plurality of offset wordline groups are regenerated based the regenerated table of error counts.

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.

Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

Abstract: A bitwise bidirectionally rewritable nonvolatile semiconductor storage device capable of performing a high-speed data rewrite, while enhancing endurance characteristics and data-retention characteristics of a memory cell. To achieve high-speed generation of rewrite-bit information indicating that a data rewrite is needed or not, the structure employs a logic circuit corresponding to the number of change patterns of write conditions and concurrently compares between read-out data RO of memory at the start of the data rewrite and prepared write data DIN. After an electrical data rewrite of the memory, the data rewrite is verified based on the rewrite-bit information stored in an internal buffer circuit. This protects an already-rewritten memory cell from unnecessary additional rewrite.

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: A spin-transfer torque magnetic random access memory (STTMRAM) cell is disclosed. The memory cell comprises a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.