Abstract: An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.

Abstract: GaN-based nanowire heterostructures have been intensively studied for applications in light emitting diodes (LEDs), lasers, solar cells and solar fuel devices. Surface charge properties play a dominant role on the device performance and have been addressed within the prior art by use of a relatively thick large bandgap AlGaN shell covering the surfaces of axial InGaN nanowire LED heterostructures has been explored and shown substantial promise in reducing surface recombination leading to improved carrier injection efficiency and output power. However, these lead to increased complexity in device design, growth and fabrication processes thereby reducing yield/performance and increasing costs for devices. Accordingly, there are taught self-organising InGaN/AlGaN core-shell quaternary nanowire heterostructures wherein the In-rich core and Al-rich shell spontaneously form during the growth process.

Abstract: Panels of LED arrays and LED lighting systems are described. A panel includes a substrate having a top and a bottom surface. Multiple backplanes are embedded in the substrate, each having a top and a bottom surface. Multiple first electrically conductive structures extend at least from the top surface of each of the backplanes to the top surface of the substrate. Each of multiple LED arrays is electrically coupled to at least some of the first conductive structures. Multiple second conductive structures extend from each of the backplanes to at least the bottom surface of the substrate. At least some of the second electrically conductive structures are coupled to at least some of the first electrically conductive structures via the backplane. A thermal conductive structure is in contact with the bottom surface of each of the backplanes and extends to at least the bottom surface of the substrate.

Abstract: A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180° phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0° and 180° clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.

Abstract: The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be ?LEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Abstract: The present disclosure provides display panels and methods for manufacturing the same. The display panel includes a pixel definition layer, a cathode, and a compensation electrode. The pixel definition layer defines a plurality of pixel definition openings and a spacing region located between two adjacent pixel definition openings of the plurality of pixel definition openings. The cathode covers the pixel definition layer. The compensation electrode is located in the spacing region. The pixel definition layer covers the compensation electrode and defines a contact hole, the cathode and the compensation electrode are connected via the contact hole.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Provided is an upper substrate for a miniature LED component, a miniature LED component, and a miniature LED display device, wherein the upper substrate for the miniature LED component comprises: a bottom substrate; a metal layer formed on the bottom substrate and having a pattern capable of covering a non-opening region of the lower substrate for the miniature LED component; a graphene layer formed on the bottom substrate; a transparent adhesive layer formed on the bottom substrate to cover the metal layer and the graphene layer.

Abstract: A display apparatus and a manufacturing method thereof. The display apparatus includes a chassis, a plurality of modular displays disposed and tiled on the chassis, each of the plurality of modular displays including a plurality of light emitting diodes (LEDs) constituting each of a plurality of pixels, and a patterned molding layer formed on the each of the plurality of modular displays, wherein the patterned molding layer is formed to correspond to a boundary line between modular displays adjacent to each other among the plurality of modular displays.

Abstract: A display device and a manufacturing method of a display device are provided. A display device includes a base substrate; an electrode on the base substrate, a light emitting element on the base substrate and electrically connected to the electrode, and a solution layer between the base substrate and the light emitting element, the solution layer including a light blocking material.

Abstract: The present disclosure is a manufacturing method for reducing non-radiative recombination of micro LED. At least one etched LED epitaxial wafer includes a plurality of etching grooves and mesas, an etched sidewall of the mesa includes a stack of a first type semiconductor layer, an active layer and a second type semiconductor layer. Two stages of ALD are performed on the etched LED epitaxial wafer with different temperature ranges. The first ALD can be used to repair dangling bonds and defects on the etched side walls of the mesa, and the second ALD can be used to form a passivation layer on the etched side walls of the mesa. By the manufacturing method of the present disclosure, non-radiative recombination of the micro LED can be reduced, and the luminous brightness and luminous efficiency of the micro LED can be improved.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a base substrate; a plurality of micro-LED groups located on the base substrate, wherein each of the plurality of micro-LED groups includes at least three micro-LEDs, and at least two micro-LEDs of each said micro-LED group have their longer sides arranged in different directions; and a shielding layer comprising a plurality of apertures located in shielding portions, wherein the shielding portions are located between adjacent micro-LEDs, and wherein the plurality of apertures each correlates one of the micro-LEDs.

Abstract: Methods of improved selectively for SAM-based selective depositions are described. Some of the methods include forming a SAM on a second surface and a carbonized layer on the first surface. The substrate is exposed to an oxygenating agent to remove the carbonized layer from the first surface, and a film is deposited on the first surface over the protected second surface. Some of the methods include overdosing a SAM molecule to form a SAM layer and SAM agglomerates, depositing a film, removing the agglomerates, reforming the SAM layer and redepositing the film.

Abstract: This specification discloses heatsinks comprising a continuous sheet of thermally conductive material folded into a structure comprising a plurality of fins defined by bends in the sheet and arranged to transfer heat to surrounding air. The sheet may be further folded to form a planar surface defined by one or more bends in the sheet and on which one or more LEDs may be mounted. Optionally, the sheet may be further folded to partially enclose the fins within a tunnel formed by side walls defined by bends in the sheet.

Abstract: A light emitting device is provided. The light emitting device includes a package structure, a first light emitting chip, a second light emitting chip, a third light emitting chip, a first encapsulant, a second encapsulant, and a third encapsulant. The first light emitting chip, the second light emitting chip, and the third light emitting chip are disposed in a first cavity, a second cavity, and a third cavity of a body of the package structure, and electrically connected with a first electrode pair, a second electrode pair, and a third electrode pair that are covered by the body. The first encapsulant, the second encapsulant, and the third encapsulant are filled in the first cavity, the second cavity, and the third cavity. A first opening of the first cavity is larger in size than a second opening of the second cavity and a third opening of the third cavity.

Abstract: Methods and systems for selectively depositing dielectric films on a first surface of a substrate relative to a passivation layer previously deposited on a second surface are provided. The methods can include at least one cyclical deposition process used to deposit material on the first surface while the passivation layer is removed, thereby preventing deposition over the passivation layer.

Abstract: A pixel structure including a substrate, a first conductor, a second conductor, and a plurality of dies is provided. The first conductor is disposed on the substrate and includes a plurality of first body portions extending along a first direction, a plurality of first branch portions extending along a second direction, and a plurality of second branch portions extending along the first direction. The second conductor is disposed on the substrate and includes a plurality of second body portions extending along the second direction and a plurality of third branch portions extending along the first direction. The die includes two electrodes, wherein the first branch portions are connected between the first body portions and the second branch portions, and the two electrodes are respectively connected to the first branch portions and the second body portions or respectively connected to the second branch portions and the third branch portions.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor having a first plurality of channel members, and a second GAA transistor having a second plurality of channel members. A pitch of the first plurality of channel members is substantially identical to a pitch of the second plurality of channel members. The first plurality of channel members has a first channel member thickness (MT1) and the second plurality of channel members has a second channel member thickness (MT2) greater than the first channel member thickness (MT1).