Abstract: A user station for a serial bus system. The user station includes a communication control device for controlling a communication of the user station with at least one other user station, and a transceiver device to serially transmit a transmission signal, generated by the communication control device, onto a bus, and serially receive signals from the bus. The communication control device generates the transmission signal according to a frame and inserts into the frame two check sums that include different bits of the frame in the computation. The communication control device inserts dynamic stuff bits into the frame in such a way that an inverse stuff bit is inserted into the bit stream of the frame after 5 identical bits in succession. The communication control device computes the two check sums so that a maximum of one of the two check sums includes the dynamic stuff bits in the computation.

Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

Abstract: An information processing apparatus includes a processor configured to perform processing of acquiring firmware that includes three or more binaries including a first program, a second program, and a third program and in which a download program is provided in the first program and the programs are started up in order from the first program, verifying the subsequent program by starting up the programs in order from the first program, verifying the subsequent program by the program in which the download program is not provided, and recording an error flag in a non-volatile memory area in a case where an error occurs, and recovering the error by executing the download program in a case where the error flag is recorded in the non-volatile memory area at a time of restart.

Abstract: Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.

Abstract: Techniques for detecting a modification to a configuration of a system are disclosed. For example, a method comprises the step of collecting a first data set for a system at a first time instance, wherein the first data set comprises inventory data for a configuration of the system present at the first time instance. The method compares the first data set to a second data set, wherein the second data set comprises inventory data for a configuration of the system present at a second time instance. The method obtains a third data set based on the comparison of the first data set and the second data set, wherein the third data set comprises data indicative of any differences between the inventory data for the configuration of the system present at the first time instance and the inventory data for the configuration of the system present at the second time instance.

Abstract: A host interface includes; a phase shift detector, a phases shifter, and control logic controlling operation of the phase shift detector and the phase shifter. The host interface sends a command and a clock to a device, receives a response from the device, communicates data to the device synchronously with the clock, and samples data received from the device synchronously with a modulated clock. The phase shift detector provides a shift value based on the response, and the phase shifter modulates a phase of the clock based on the shift value to generate the modulated clock.

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

Abstract: Clocks of two semiconductor circuit are set to a common clock source when both the first and second semiconductor circuits are in a slow clock speed at which an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating. Division counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed, wherein the IO is not capable of operating at the fast clock speed. Pulses from a division counter of the first circuit are sent to a spare division counter of the second circuit, and then a primary division counter of the second counter is aligned to this spare division counter to keep the two circuits synchronized at the fast clock speed.

Abstract: A field programmable gate array (FPGA) including a configurable interconnect fabric connecting a plurality of logic blocks, the configurable interconnect fabric and the logic blocks being configured to implement a data masking circuit configured to: receive input data including data values at a plurality of indices of the input data; select between a data value of the data values and an alternative value using a masking multiplexer to generate masked data, the masking multiplexer being controlled by a mask value of a plurality of mask values at indices corresponding to the indices of the input data; and output the masked data. In some examples, the configurable interconnect fabric and the logic blocks are further configured to implement a mask generation circuit configured to generate the mask values. In some examples, the mask values are received from external memory.

Abstract: Systems and methods for providing a Basic Input/Output System (BIOS) enforced blocklisting of harmful applications are described. In one embodiment, an Information Handling System (IHS) may include a processor and a BIOS coupled to the processor, the BIOS having program instructions that, upon execution, cause the IHS to download an Unsafe Application List (UAL) from an online source, and during a bootstrap process of the IHS, compare a plurality of Applications (Apps) installed on the IHS against a list of harmful applications included in a UAL. When a harmful application is found by the comparison, the instructions enforce one or more policies to restrict the harmful application from being executed on the IHS.

Abstract: In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. A selection line for each one of the slave devices couples the master device with a respective slave device and is dedicated to selection by the master device of the respective slave device for communication over the shared data communication bus. Each of the slave devices is able to send an interrupt request to the master device over the respective selection line to be served by the master device initiating a communication over the shared data communication bus, each selection line thereby being a bidirectional communication line between the respective slave device and the master device.

Abstract: A hardware functional module sends, to an aggregation module and in a standardized message format, first status information associated with the hardware functional module according to a first set of reporting rules via a first dedicated link. The firmware functional module sends, to the aggregation module and in the standardized message format, second status information associated with the firmware functional module according to a second set of reporting rules via a second dedicated link. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and inserts a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream enables a visualization system to analyze the hardware functional module and the firmware functional module.

Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

Abstract: A message inspection engine, implemented in hardware in a System on Chip (SOC), is configured using configuration information to obtain a configured message inspection engine. An input message is received at the configured message inspection engine from an upstream functional module in the SOC. The configured message inspection engine is used to analyze the input message to determine a content modification plan and a destination control plan and to generate an output message based at least in part on the input message, the content modification plan, and the destination control plan, including by populating the output message with a downstream functional module specified by the destination control plan. The output message is output from the configured message inspection engine.

Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.

Abstract: An open compute project (OCP) adapter card and a computer device are disclosed. The adapter card includes an OCP connector, a controller, a selector, and a motherboard connector. The OCP connector is configured to connect to an OCP network interface card (NIC). The controller is configured for bandwidth allocation, in-situ control and power-on/off control of the OCP NIC. The selector gates a single-homed host or a dual-homed host based on working mode configuration information stored in the controller. The motherboard connector is configured to connect to a motherboard device.

Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: A synchronization trigger associated with synchronizing credit is obtained at a message receiver in a System On Chip (SOC). In response to receiving the synchronization trigger, a value for a local credit in the message sender is sent from the message receiver to a message sender in the SOC. At the message sender, the local credit is updated with the value for the credit that is received from the message receiver, wherein a requirement to send a message from the message sender to the message receiver is that the local credit has a non-zero value.

Abstract: Aspects of a storage device are provided which delay thermal throttling in response to temperature increases based on different reliable temperatures for different types of cells, such as SLCs, hybrid SLCs and MLCs. Initially, a controller writes first data to a block of MLCs at a first data rate when a temperature of the block meets a first temperature threshold for MLCs. Subsequently, the controller writes second data to the block at a second data rate lower than the first data rate when the temperature of the block meets a second temperature threshold for SLCs. For hybrid SLCs, the MLCs are each configured to store a first number of bits, and the controller writes a second number of bits smaller than the first number of bits in each of one or more of the cells. Storage device performance is thus improved through delayed thermal throttling without compromising data integrity.