Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: A synchronization trigger associated with synchronizing credit is obtained at a message receiver in a System On Chip (SOC). In response to receiving the synchronization trigger, a value for a local credit in the message sender is sent from the message receiver to a message sender in the SOC. At the message sender, the local credit is updated with the value for the credit that is received from the message receiver, wherein a requirement to send a message from the message sender to the message receiver is that the local credit has a non-zero value.

Abstract: Aspects of a storage device are provided which delay thermal throttling in response to temperature increases based on different reliable temperatures for different types of cells, such as SLCs, hybrid SLCs and MLCs. Initially, a controller writes first data to a block of MLCs at a first data rate when a temperature of the block meets a first temperature threshold for MLCs. Subsequently, the controller writes second data to the block at a second data rate lower than the first data rate when the temperature of the block meets a second temperature threshold for SLCs. For hybrid SLCs, the MLCs are each configured to store a first number of bits, and the controller writes a second number of bits smaller than the first number of bits in each of one or more of the cells. Storage device performance is thus improved through delayed thermal throttling without compromising data integrity.

Abstract: Emulated telemetry interfaces for host processors and management processors coupled over communication fabrics are presented herein. In one example, an apparatus includes a monitoring function executed by a host processor configured to determine telemetry related to operation of at least the host processor. A driver function executed by the host processor is configured to emulate operation of a network interface to an operating system of the host processor for transfer of communications comprising at least the telemetry to a management processor over a communication fabric different than the network interface, where the host processor and the management processor are communicatively coupled to the communication fabric.

Abstract: A universally-designed control circuit for communicating with multiple types of sensors is disclosed. For example, a control circuit may communicate with either ring oscillator-based sensors or BJT-based sensors based on programming implemented in the control circuit. The control circuit may include programmable communication protocol circuits for communicating with the sensors and conversion circuits that convert a particular type of sensor data packet into a generic format. The generic format sensor data may then be utilized by a power management unit or other device to control operation of an integrated circuit.

Abstract: In an embodiment, an example computer-implemented method for configuring a hardware accelerator to perform a non-linear function involves: determining a plurality of intervals that partition an input domain of the non-linear function; determining a plurality of subinterval configurations corresponding to different numbers of subintervals for partitioning that interval; generating an error set comprising an error for using a polynomial function to approximate the non-linear function within one or more corresponding subintervals specified by the subinterval configuration; using the error set and resource constraints, selecting one of the subinterval configurations for each of the intervals to generate a configuration set that minimizes a worst-case error across the intervals; selecting one of the subinterval configurations for each of the intervals to generate an improved configuration set that minimizes a cumulative error across the intervals without exceeding the worst-case error; and configuring the hardware

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

Abstract: Systems and techniques for automated transfer of peripheral device operations are described herein. In an example, a system may adapted so that, while a first device of a first type and a second device of the first type are simultaneously connected to a client device, the first device, rather than the second device, is used as an active device of the first type for at least one application, the first and second devices being peripheral devices. The system may be further adapted so that, while both the first and second devices remain connected to the client device, a switch from the first device to the second device by a user is determined, and, based on the switch from the first device to the second device, the second device, rather than the first device, is used as the active device of the first type for the at least one application.

Abstract: An adapting device according to an embodiment includes: a first storage unit configured to store correspondence information representing a correspondence relation between processing requested by a higher-level system and a method for implementing the processing in a lower-level system; a conversion unit configured to convert a processing request from the higher-level system to the lower-level system into a processing procedure capable of being implemented in the lower-level system and supply the processing procedure to the lower-level system; and an additional information processing unit configured to generate additional information to be supplied to the lower-level system together with the processing procedure.

Abstract: An all-in-one computer includes a display, a Universal Serial Bus (USB) Type-C port, a plurality of USB Type-A ports, a USB hub, a demultiplexer, and a Power Delivery (PD) controller. The USB hub is coupled to the plurality of USB Type-A ports. The demultiplexer is coupled between the display, the USB Type-C port, and the USB hub. The PD controller is to control the demultiplexer and the USB hub to pass a display signal input to the USB Type-C port to the display and pass signals input to the USB hub from the plurality of USB Type-A ports to the USB Type-C port with a computing device coupled to the USB Type-C port.

Abstract: A portable electronic device includes a main system circuit, a storage, a power button, a power-off trigger circuit, a system power-off circuit, a power supply circuit, and a configuration power-off circuit. The power-off trigger circuit is coupled to the power button and provides a system power-off signal and a configuration power-off signal when the power button is detected to be continuously pressed and a pressing time is greater than a predetermined time. The system power-off circuit is coupled to the power-off trigger circuit and the power supply circuit and stops providing the main system circuit with a system power supply voltage provided by the power supply voltage according to the system power-off signal. The configuration power-off circuit is coupled to the power-off trigger circuit and the storage and drives the configuration power supply voltage provided to the storage down to a ground voltage according to the configuration power-off signal.

Abstract: A bus arrangement includes a coordinator, a first subscriber having a first optical display, a second subscriber having a second optical display, a third subscriber having a third optical display, and a bus that couples the coordinator to the first, second, and third subscribers. In a standard operating phase, the first subscriber is configured to display first local information of the first subscriber on the first optical display, the second subscriber is configured to display second local information of the second subscriber on the second optical display, and the third subscriber is configured to display third local information of the third subscriber on the third optical display. The coordinator is configured to switch from a standard operating phase to a display operating phase based on detecting a fault in the first subscriber.

Abstract: Disclosed are a data transmission apparatus and method, used for transmitting data between a transmitter and a receiver connected by N data lines, N being an integer greater than 1. The method comprises: sending a plurality of data units one by one; on each transmission signal, inverting the level of one and only one data line corresponding to the currently sent data unit; extracting the transmission signal, and decoding the data unit corresponding to the data line according to the data line of which level is inverted among the N data lines; and sampling the data unit and then outputting.

Abstract: A storage device is provided. The storage device includes a field programmable gate array board connected to a first port of the storage device; and a storage controller including a first interface circuit and a second interface circuit. The first interface circuit is connected to the FPGA board, the second interface circuit is connected to a second port of the storage device, at least one port from among the first port and the second port being configured to connect to an external storage device, and the FPGA board is configured to provide a path for transferring data in a peer-to-peer manner between the storage controller and the external storage device without intervention of a host.

Abstract: One embodiment facilitates measurement of a performance of a storage device. During operation, the system determines a normalized cost for an I/O request, wherein the normalized cost is independent of an access pattern and a type of the I/O request, wherein the normalized cost is indicated by a first number of virtual I/O operations consumed by the I/O request, and wherein a virtual I/O operation is used as a logical unit of cost associated with physical I/O operations. The system identifies a performance metric for the storage device by calculating a second number of virtual I/O operations per second which can be executed by the storage device. The system allocates incoming I/O requests to the storage device based on the performance metric, e.g., to satisfy a Quality of Service requirement, thereby causing an enhanced measurement of the performance of the storage device.

Abstract: A machine automation system for controlling and operating an automated machine. The system includes a controller and sensor bus including a central processing core and a multi-medium transmission intranet for implementing a dynamic burst to broadcast transmission scheme where messages are burst from nodes to the central processing core and broadcast from the central processing core to all of the nodes.

Abstract: A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

Abstract: Removeable couplings are provided for connecting a memory module to a host processor of an IHS (Information Handling System). The coupling includes electrical contacts and fasteners for positioning the electrical contacts within an empty memory slot of the IHS motherboard. The housing extends between two ends of the coupling and receives the memory module when the memory module is installed in the IHS. The positioned electrical contacts are then seated within the memory slot of the motherboard by the downward force applied by an administrator in installing the memory module to the coupling. The force applied in installing the memory module also serves to connect the electrical contacts of the coupling to a memory channel of the motherboard. The removeable coupling is not attached to the motherboard when the memory module is not installed in the IHS, thus eliminating signal stubs in the memory channel.

Abstract: Provided is an extension module for independently storing calibration data, including: a first interface, adapted to receive a first external input signal; a second interface, adapted to output the first output signal of the extension module; a signal processing circuit, connected between the first interface and the second interface; and a first memory, the first memory storing first calibration data, and the first calibration data being associated with the extension module. Furthermore, also provided is a component using the above extension module, and a component calibration method. On the one hand, the extension module of an embodiment may share an ADC sampling circuit on a main module, so that the manufacturing cost of the extension module is reduced. On the other hand, an embodiment can facilitate the replacement of different extension modules for the main module without repeated calibration.