Abstract: Disclosed are devices and methods, among which is a device peripheral to a controller device that is used to provide memory access to the controller device. In some embodiments, the device may determine and provide a response of the device to requests from the separate device.

Abstract: Modular transaction terminal services are provided. The services are customized for specific features using configuration data maintained in files. The services communicate using a standardized data format and Application Programming Interface (API). An interface is provided for custom defining an instance of a processing environment for a target transaction terminal. Customizations are made to the files and process flow data structures that are processed by the services. The hardware requirements of the target transaction terminal are also obtained and an installation package is created for the target transaction terminal. The installation package is installed on hardware of the target transaction terminal and the processing environment initiated. The services, configuration data maintained in files, process flow data structures, and interface represent a modularized and customizable transaction terminal architecture.

Abstract: As described herein, a method performed in response to a client device undergoing an at least partial warm reset or reboot may include receiving a firmware commit request from a client device. The method may also include writing, at a first time, a firmware image associated with the client device into execution memory of volatile memory. The method may also include writing, at a second time, the firmware image associated with the client device into a memory slot of non-volatile memory.

Abstract: Described is an architecture for a physical layer device useable with single pair Ethernet in a multidrop bus topology that may operate in a sleep mode and control other devices in network segment to operate in a sleep mode. Some embodiments of the physical layer device may support partial networking in a multidrop network, and mixed networks including the same.

Abstract: A thread executing a task at a node in a multi-socket computing system may access a first data structure to obtain a first calibration dataset for the node. The first thread may generate a timestamp based on the first calibration dataset and a first quantity of time measured by a clock at the first node. The real-time duration of the task may be determined based on the timestamp. The first thread may recalibrate the first clock by at least generating, based on the first quantity of time measured by the clock and a second quantity of time measured by a wall clock of an operating system of the multi-socket computing system, a second calibration dataset. The first thread may update the first data structure to include the second calibration dataset while a second thread accesses a second data structure to obtain calibration data.

Abstract: The methods and systems may provide a scalable round-robin arbiter tree that performs round-robin arbitration for a plurality of requests received from a set of requestors. The round-robin arbiter may stack a plurality of round-robin cells in stages where an output of a first stage of round-robin cells is an input to a next stage of round-robin cells. The round-robin arbiter may transform an arbitration state at each stage of the arbitration and propagate the arbitration state into the next stage for arbitration. The arbitration state from the final stage round-robin cell is fed back to the first stage of the round-robin cells and used in a subsequent arbitration round.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include ports to receive requests from a host and to send requests to a second storage device. The SSD may include flash storage for data. An SSD controller may process the requests received from the host and generate the requests sent to the second storage device. The SSD may act as a cache for the second storage device.

Abstract: Systems and methods for network port monitoring using low energy wireless communications are provided. In one embodiment, a device comprises: at least one port module, the at least one port module comprising one or more connector ports each configured to receive a connector of a network data cable; and a port state sensor that includes a port sensing circuit coupled to a sensor controller, wherein the port sensing circuit is configured to sense a port state for the one or more connector ports; wherein the sensor controller is configured to input the port state from the port sensing circuit, wherein in response to detecting a change in the port state from the port sensing circuit, the sensor controller wirelessly transmits port state information to a port state monitor.

Abstract: A wireless gaming keyboard and mouse adapter system may comprise a wireless gaming keyboard and mouse adapter housing, forming a dongle operably coupled to an input device, within which an electrical circuit and an antenna are embedded within a plurality crystal polymer layers for housing a network interface device, a USB-C adapter mounting, and a controller, which may be electrically coupled via the electrical circuit, and where the network interface device is electrically coupled to the antenna. The controller may receive input/output gaming instructions for the gaming software application, via the USB-C adapter, from an input device for a remote information handling system executing the gaming software application, and may execute wireless gaming keyboard and mouse adapter system code instructions to direct the network interface device to transceive the input/output gaming instructions to a cloud-based gaming application server via the wireless network Access Point (AP) at frequencies above 24 GHz.

Abstract: Innovative techniques to efficient stripe ordered writes across multiple socket-to-socket links. The ordered writes may be PCIe ordered writes. Each socket-to-socket write (or remote write) for an address may be converted into two transactions. The first transaction may ensure that coherency for the address is ensured. The second transaction may be the actual request transaction to write the data of the address. In so doing, when multiple remote writes are involved, the remote writes may be distributed over multiple socket-to-socket links to maximize bandwidth.

Abstract: Described herein are systems and methods for object detection to achieve hard real-time performance with low latency. Real-time object detection frameworks are disclosed. In one or more embodiments, a framework comprises a first CPU core, a second CPU core, and a plurality of shaves. In one or more embodiments, the first CPU core handles general CPU tasks, while the second CPU core handles the image frames from a camera sensor and computation task scheduling. In one or more embodiments, the scheduled computation tasks are implemented by the plurality of shaves using at least one object-detection model to detect an object in an image frame. In one or more embodiments, computation results from the object-detection model with a higher detection probability is used to form an output for object detection. In one or more embodiments, the object-detection models share some parameters for smaller size and higher implementing speed.

Abstract: A power over Ethernet (PoE) power supplying method where power sourcing equipment (PSE) and a powered device exchange link layer discovery protocol data units (LLDPDUs). Each of the LLDPDUs includes two power values. Each of the power values indicates requested or allocated power for one of two sets of cable pairs of the Ethernet twisted pair connecting the PSE and the powered device. Accordingly, the supplied powers to the powered device at sets of cable pairs are independent from each other.

Abstract: C-state transitions due to software timer interrupts can be minimized. A timer interrupt synchronizer can be deployed on a computing device to function as an intermediary between software components that rely on timer interrupts and a timer interrupt architecture of the computing device. When the software components request timer interrupts, the timer interrupt synchronizer can ensure that timer interrupts having the same frequency can be synchronized to occur at the same time. As a result of this synchronization, a CPU can experience fewer C-state transitions due to the timer interrupts.

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

Abstract: Techniques related to hosted client management comprising providing a hosted client instance over a network interface for communicatively coupling with a remote client device, the hosted client instance including a first application component for performing a first plurality of actions associated with the hosted client instance and a second application component for performing a second plurality of actions, monitoring, by the first application component, the second application component for an event associated with the second application component, determining that the event impacts the first application component based on one or more dependency tables associated with the second application component, and displaying, in a user interface of the first application component, information related to the event.

Abstract: A non-transitory computer-readable storage medium may be executable by a processor to receive a designation of a message bus producer, a set of business logic to be stored in a set of containers, a designation of a message bus consumer, and a designation of a set of message-handling functions. The non-transitory computer-readable storage medium may generate a serverless application stack, based upon the message bus producer, the set of business logic, the message bus consumer, and the set of message-handling functions. The non-transitory computer-readable storage medium may cause the serverless application stack to receive a message stream from the message bus producer as streaming data, process the message stream according to at least one function, stored in the set of containers, perform at least one message-handling function of the set of message-handling functions on the message stream, and transport the set of messages to the message bus consumer.

Abstract: Embodiments of systems and methods for platform framework arbitration are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: provide, from a platform framework to an arbitration object via an Application Programming Interface (API), a plurality of runtime objects; receive, by the platform framework from the arbitration object via the API, an indication of an arbitration result with respect to the plurality of objects; and convey, from the platform framework to a participant via the API, the indication of the arbitration result.

Abstract: A method for data transmission control of inter field programmable gate array (FPGA) and an associated apparatus are provided. The method includes: utilizing a first register device to latch a set of data from a first FPGA according to a first clock, wherein the set of data is arranged and divided into multiple sets of partial data according to attributes of payloads and pointers; utilizing a time-division multiplexing (TDM) interface to transmit the multiple sets of partial data from the first register device to a second register device according to a TDM clock at multiple time points, respectively; and utilizing the second register device to sequentially receive the multiple sets of partial data, in order to output the set of data to a second FPGA, wherein the second FPGA operates according to a second clock different from the first clock.

Abstract: Embodiments described herein are generally directed to a configuration-driven continuous delivery (CD) pipeline that can be used by multiple development teams and integrated with multiple repositories. According to an example, all commands to be run by a particular executor used by a particular development team are specified by the pipeline. A trigger event is received from an external source specifying a repository in which source code for an application being developed or maintained by the particular development team resides. Responsive to the trigger event, the pipeline is configured with information regarding subdirectories within the repository that are to be processed based on a first set of configuration information stored in the repository. Stages of the pipeline are performed by, for each subdirectory, causing the pipeline to issue a subset of the commands to the particular executor based on a second set of configuration information associated with the subdirectory.

Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry having receiver circuitry to receive refresh signals during corresponding refresh cycles from a link partner during a low-power idle mode of operation. Each refresh signal has a refresh period, and where a quiet period is interposed between successive refresh cycles. Signal quality detection circuitry, during the low-power idle mode, determines a measure of signal quality associated with the received refresh signals. Subsequent refresh cycles exhibit at least one of an adjusted refresh period or an adjusted quiet period based on the measure of signal quality.