Abstract: A network relay device compliant with network plug-and-play protocols is presented. The relay device relays messages between a network and a device unit having N service devices that provide a service in response to a request from a client on the network. In one embodiment the relay device has a description creating module configured to create a device description which describes service devices included in the device unit connected to the relay device. If one or more service devices of the device unit are inoperative, the description creating module creates a device description that does not include a description portion of the inoperative service devices and forwards the created device description to the client. In another embodiment, the relay device has a response module configured to respond to a device search request sent from a client.

Abstract: The present invention discloses a signal processing system applicable in an electronic system having a hard disk, an indicator and an I/O controller, the I/O controller processing a driving signal outputted by the hard disk and generating a first processing signal. The signal processing system includes an editing module for editing a plurality of decoding modes, a detecting module for detecting a type of the I/O controller and outputting type messages corresponding to the detected type of the I/O controller; an acquiring module for acquiring the decoding mode from the editing module according to the type messages outputted by the detecting module; and a decoding module for decoding the first processing signal outputted by the I/O controller according to the decoding mode acquired by the acquiring module and generating a second processing signal to drive the indicator to operate, thereby simplifying the design and reducing the cost.

Abstract: A data processing apparatus stops a supply of data to a buffer when the buffer becomes full, and thereafter performs processing such as moving to a low-power mode and switching execution tasks. The data processing apparatus then reverts from the low-power mode and resumes execution of a task for supplying data to the buffer when a predetermined reversion condition is satisfied. The predetermined reversion condition is that, for example, processing with respect to data in a predetermined data cluster is completed, a predetermined time period has elapsed, or a cycle handler notifies an event occurrence.

Abstract: A DMA circuit prevents an erroneous data transfer by a descriptor due to an address failure of memory. When a descriptor is created, the data processing unit writes a pointer, for storing the descriptor, in a predetermined part of the descriptor, and stores the descriptor in memory, and when a DMA engine reads the descriptor from the memory, the DMA engine confirms whether the value is correct, and judges whether a DMA transfer of the data in the memory is possible. For both reading and writing of a descriptor, data corruption due to an address failure can be prevented.

Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

Abstract: An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point connection, and a control unit that issues a request command based on a request synchronization signal for data with a timing constraint on line synchronous transfer by a line synchronization signal to transmit a plurality of data, including the data with the timing constraint, simultaneously via the high-speed serial bus.

Abstract: According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: The present invention is directed to a method and system for providing, transparent mixed mode, object and block data storage transport. The system implements I/O modules capable of translating between communication protocols for providing common message passing multi-channel data transport for data storage while providing apparent I/O circuit exclusivity to controllers. The system is capable of converting object based transports for block storage, thus permitting both block and object based access to the storage complex. Implementing the system of the present invention allows for a common data transport system permitting component scalability and virtualization while allowing for target and initiator mode utilization of I/O interface circuits.

Abstract: A network storage system includes a non-volatile memory to store data including a log of received data access requests, and a cluster interconnect adapter through which to send data to a cluster partner. The nonvolatile memory and the cluster interconnect adapter are implemented in a single device connected to an expansion bus in the network storage system. Communication with the nonvolatile memory is carried out using LDMA, and communication with the cluster partner is carried out using RDMA via the cluster interconnect adapter. LDMA and RDMA functionality are merged in a common software stack.

Abstract: A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the total number of such context switches. The threshold mechanism is associated with a buffer into which the producer stores packets up to a given threshold before the consumer is allowed to remove packets. The buffer has an associated upper limit on the number of packets that can be stored in the buffer. A flush empties the buffer of any remaining packets when no more packets are to be produced. This reduction in the total number of context switches in general leads to better performance at the cost of more latency.

Abstract: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.

Abstract: Since no control of accesses made by a computer as accesses to a storage apparatus is executed, the computer can be used illegally to steal and improperly change data stored in the storage apparatus. Thus, an access-control mechanism external to the computer is constructed to solve this problem. That is to say, the control of accesses is executed in the storage apparatus and a network apparatus for each program executed by the computer. In order to enhance the implementability of such control of accesses, the control is executed without extending a variety of protocols of communications among the computer, the network apparatus and the storage apparatus. By implementing the control of accesses in this way, a program other than programs specified in advance is not capable of making an access to data stored in the storage apparatus. Thus, even if the computer is used illegally, data stored in the storage apparatus can be prevented from being stolen and changed improperly.

Abstract: Techniques for supporting optical and electrical protocols, such as on the ports of a line card in a network device, are provided. A port on a line card supports optical and electrical connections. The PHY monitors a signal to determine if the transmission connection at the port has changed, such as from optical to electrical, or vice versa. If there has been a change, the PHY is directed to reset a port to correspond to the appropriate transmission connection. By resetting the port, the PHY changes the protocol that is utilized with the signals (e.g., NRZI or 3-Level MLT3).

Abstract: A method and apparatus are described for providing initialization in large storage systems as a background function, upon demand, and upon receipt of write requests. The initialization may be carried out under control of the hard disk drive itself, a storage controller, or both systems. The initialization is performed transparently to the host computer making operation of the storage system immediately after it is coupled to the host feasible.

Abstract: According to one embodiment, a system is disclosed. The system includes an input/output (IO) frame manager (IOFM) to route received IO frames to one or more IO lists and one or more IO frame order managers (IOFOMs) to reorder frames received for each IO list according to a relative order.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.

Abstract: A storage control device 2A includes a host interface control unit 3, a storage control firmware A, and electrically rewritable non-volatile memory 7 and, using non-volatile memory 7, stores necessary information during exchange of an activation program of the storage control firmware A, and using the information exchanges the activation program without disconnection to a host 1 and without erroneous response to a command from the host 1.

Abstract: An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.

Abstract: The invention relates to a method for use in a system comprising a host device and at least one peripheral device which are enabled to interact with each other. In order to improve the flexibility of the system, the method comprises a step of transmitting information indicative of a time required for an initialization of the at least one peripheral device from the at least one peripheral device to the host device, and a step of evaluating in the host device the information indicative of a time required by the at least one peripheral device for an initialization. The invention relates equally to a corresponding host device, to a corresponding peripheral device, to a corresponding system and to corresponding software program products.