Abstract: The present invention variably controls the packet size that is used within a storage device in accordance with the communication environment outside the storage device. The storage device comprises a CHA that controls data transfers with a host and a DKA that controls data transfers with a disk drive. The upper level I/F judgment unit of the CHA judges the type and communication band of the communication protocol used by the host and the packet size setting unit sets the optimum packet size on the basis of the type of communication protocol thus identified, and so forth. Likewise, the DKA sets the optimum packet size on the basis of the type and data processing speed of the disk drive that is used. As a result, data can be shifted rapidly to a packet in exchanges between the host and cache memory and between the disk drive and cache memory, whereby the data transfer efficiency can be improved.

Abstract: A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.

Abstract: When the destinations of local electrical signals are local computers, the local electrical signals are transmitted to the corresponding destination local computers via the keyboard video mouse (KVM) switch directly. When the destinations of the local electrical signals are remote computers, at least one network packet having multiple data sections for correspondingly storing the local electrical signals is generated by the current KVM switch referring to the local electrical signals. A communication is established among a plurality of the KVM switches using a network protocol, for communicating the network packets thereof. At least one remote electrical signal is obtained from another network packet transmitted by another KVM switch, and then is transmitted to the corresponding destination local computer.

Abstract: Systems and methods are provided for authentication by combining a Reverse Turing Test (RTT) with password-based user authentication protocols to provide improved resistance to brute force attacks. In accordance with one embodiment of the invention, a method is provided for user authentication, the method including receiving a username/password pair associated with a user; requesting one or more responses to a first Reverse Turing Test (RTT); and granting access to the user if a valid response to the first RTT is received and the username/password pair is valid.

Abstract: Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.

Abstract: A semiconductor integrated circuit apparatus capable of reading out semiconductor information stored therein is provided. A semiconductor information storage section has semiconductor information unique to a semiconductor integrated circuit apparatus stored therein. The unique semiconductor information includes, for example, an identification number for identifying the semiconductor integrated circuit apparatus and information for identifying the time of manufacture such as a lot number. An externally provided storage apparatus has a readout program stored therein for reading the semiconductor information of the semiconductor integrated circuit apparatus as required.

Abstract: A processor includes a plurality of input ports, memory circuitry for storing data blocks associated with protocol data units (PDUs) and received by the processor at the input ports, and controller circuitry coupled to the memory circuitry. The controller circuitry is operative to discard certain ones of the data blocks received at the input ports in an oversubscription condition in which the received data blocks exceed a designated capacity of the processor. A discarded data block indicator is generated for a given one of the input ports if a data block received at the given input port for a particular PDU is discarded. One or more additional data blocks received at the given input port for the particular PDU are discarded based at least in part on the discarded data block indicator. The oversubscription condition may thereby be overcome in a manner which advantageously minimizes the number of received PDUs that are corrupted through discarded data blocks.

Abstract: Buffer control means and output control means are included within a buffering apparatus. Data longer than the width of data bus is read by single access from buffer means. Rather than signal line control for each bus width, signal line control for each data group is performed by a method wherein address administration means holds address information in relationship with each group of a series of data written in the buffer means and data is output from the buffer means.

Abstract: The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.

Abstract: A data transferring apparatus for transferring liquid ejection data has a decoding unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for storing the liquid ejection data developed by a word unit and a compressed data inputting unit for transferring the liquid ejection data from an external part to the decode circuit.

Abstract: A separator pad for stacked containers is composed of a spunbonded central fabric of polypropylene having a basis weight of 6 to 11 oz. per square yard and outer flat layers of polypropylene.