Abstract: The present invention provides a Group III nitride semiconductor light-emitting device which prevents an increase in driving voltage, and which has low threading dislocation density as a whole. The light-emitting device includes an embossed substrate. The substrate has, on a main surface thereof, a first region in which protrusions are arranged at a small pitch, and second regions in which protrusions are arranged at a large pitch. The second regions correspond to projection areas of a p-pad electrode and an n-pad electrode as viewed through the main surface of the substrate. The first region corresponds to a projection area, as viewed through the main surface of the substrate, of a region in which neither the p-pad electrode nor the n-pad electrode is formed.

Abstract: A light emitting element has a semiconductor layer, a pair of positive and negative electrodes, and a reinforcing portion. The pair of positive and negative electrodes is disposed on a lower face side of the semiconductor layer. The pair of electrodes is connected to the substrate. The reinforcing portion is disposed on an outer edge part of an upper face of the semiconductor layer. The reinforcing portion is made from a light-transmissive material. The upper face includes an exposed portion exposed from the reinforcing portion.

Abstract: Provided are a method of fabricating a light-emitting apparatus with improved light extraction efficiency and a light-emitting apparatus fabricated using the method. The method includes: preparing a monocrystalline substrate; forming an intermediate structure on the substrate, the intermediate structure comprising a light-emitting structure which comprises a first conductive pattern of a first conductivity type, a light-emitting pattern, and a second conductive pattern of a second conductivity type stacked sequentially, a first electrode which is electrically connected to the first conductive pattern, and a second electrode which is electrically connected to the second conductive pattern; forming a polycrystalline region, which extends in a horizontal direction, by irradiating a laser beam to the substrate in the horizontal direction such that the laser beam is focused on a beam-focusing point within the substrate; and cutting the substrate in the horizontal direction along the polycrystalline region.

Abstract: A power semiconductor module includes an element pair formed by connecting, in anti-parallel to each other, an IGBT and an FWD group in which an FWD, a voltage drop characteristic of which during conduction has a negative temperature coefficient, and an FED, a voltage drop characteristic of which during conduction has a positive temperature coefficient, are connected in series and an element pair formed by connecting, in anti-parallel to each other, an IGBT and an FWD group in which a FWD, a voltage drop characteristic of which during conduction has a negative temperature coefficient, and an FWD, a voltage drop characteristic of which during conduction has a positive temperature coefficient, are connected in series. The element pairs are connected in parallel.

Abstract: A light-emitting device includes: a Distributed Bragg reflector comprising alternate first semiconductor layers and second semiconductor layers, wherein each first semiconductor layer comprises a low-refractive-index part having a depth; and a light-emitting semiconductor stack associated with the Distributed Bragg reflector; wherein the depths of the low-refractive-index parts of the first semiconductor layers are gradually changed in a direction toward the light-emitting semiconductor stack.

Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.

Abstract: Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region. Source/drain regions are provided at both sides of the active region under the gate electrode, respectively. A width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode.

Abstract: An array substrate includes; a substrate, a gate line and a data line disposed on the substrate, a thin film transistor (“TFT”) electrically connected to the gate line and the data line, a light blocking member disposed on the substrate and a first color filter and a second color filter disposed on the substrate. The light blocking member covers a portion of the first color filter and the second color filter covers a portion of the light blocking member.

Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

Abstract: As an example, a value obtained by adding the magnitudes of a plurality of angular velocities around respective axes indicated by angular velocity data obtained from an input device including gyroscopic sensors, is used to calculate a rotation parameter indicating a rotation amount. A predetermined object which is rotated, depending on the rotation amount corresponding to the rotation parameter, is displayed on a display device. As another example, when it is determined, based on the angular velocity data, that the attitude of the input device is stable, a stability flag which indicates that the attitude of the input device has been at least once stable is set and updated to ON. When there is an input device whose stability flag is OFF, the aforementioned determination is performed and a screen including a result of the determination is displayed on a display device.

Abstract: An electric contact structure adopted for an LED comprises a nitride middle layer and an N-type metal electrode layer. The LED includes an N-type semiconductor layer, a light emission layer and a P-type semiconductor layer that are stacked to form a sandwich structure. The nitride middle layer is patterned and formed on the N-type semiconductor layer. The N-type metal electrode layer is formed on the nitride middle layer and prevented from being damaged by diffusion of the metal ions as the nitride middle layer serves as a blocking interface, thus electric property of the N-type semiconductor layer can be maintained stable. The nitride middle layer would not be softened and condensed due to long-term high temperature, thereby is enhanced adhesion. Moreover, the N-type metal electrode layer further can be prevented from peeling off, hence is increased the lifespan of the LED.

Abstract: A laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) includes: a source contact region, a gate contact region, a drain contact region, and an n-type buried layer. The LDMOSFET also includes a p-type body region formed in an n-type epitaxial layer, the p-type body region directly contacting the source contact region and extending past an end of the source contact region toward the drain contact region. The LDMOSFET also includes a p-type reduced surface field (PRSF) region formed in the n-type epitaxial layer, the PRSF region disposed between the p-type body region and the n-type buried layer. The LDMOSFET also includes an n-type drift region formed in the n-type epitaxial layer, the n-type drift region directly contacting the drain contact region. The LDMOSFET also includes an n-type diffusion region in the n-type epitaxial layer, the n-type diffusion region electrically connecting the n-type buried layer with the n-type drift region.

Abstract: A laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) includes a p-type body region formed in an n-type epitaxial layer, the p-type body region directly contacting a source contact region and extending past an end of the source contact region toward a drain contact region. The LDMOSFET also includes a p-type reduced surface field (PRSF) region formed in the n-type epitaxial layer, the PRSF region disposed between the p-type body region and the n-type buried layer. The LDMOSFET also includes an n-type drain drift region formed in the n-type epitaxial layer, the n-type drain drift region directly contacting the drain contact region. The LDMOSFET also includes an n-type drift region formed in the n-type epitaxial layer, the n-type drift region directly contacting the n-type drain drift region.

Abstract: A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.

Abstract: An IMM solar cell and an associated method of fabricating an IMM solar cell are provided. In the context of a method, a first subcell may be formed upon a temporary substrate and a second subcell may be formed upon the first subcell. The second subcell may have a smaller band gap than the first subcell. The method may also bond the first and second subcells to a silicon subcell and then remove the temporary substrate. In the context of an IMM solar cell, the IMM solar cell includes first and second subcells with the first subcell disposed upon the second subcell and the second subcell having a smaller band gap than the first subcell. The IMM solar cell may also include a silicon subcell supporting the first and second subcells thereupon with a metal-to-metal bond between the silicon subcell and the second subcell.

Abstract: Magnetic sensors are disclosed, as well as methods for fabricating and using the same. In some embodiments, an EMR effect sensor includes a semiconductor layer. In some embodiments, the EMR effect sensor may include a conductive layer substantially coupled to the semiconductor layer. In some embodiments, the EMR effect sensor may include a first voltage lead coupled to the semiconductor layer. In some embodiments, the first voltage lead may be configured to provide a voltage for measurement by a voltage measurement circuit. In some embodiments, the EMR effect sensor may include a second voltage lead coupled to the conductive layer. In some embodiments, the second voltage lead may be configured to provide a voltage for measurement by a voltage measurement circuit. Embodiments of a Hall effect sensor having the same or similar structure are also disclosed.

Abstract: Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.

Abstract: A light emitting semiconductor device according the invention includes an SOI substrate, a collector and an injector. The SOI substrate includes a carrier layer, a buried oxide layer on the carrier layer, and a doped silicon layer structure with a conductivity type. The doped silicon layer structure with the conductivity type includes at least two silicon- or silicon germanium layers arranged adjacent to one another, wherein a dislocation network is configured in their interface portions at which dislocation network a radiative charge carrier combination with a light energy is provided, which light energy is smaller than a band gap energy of the silicon- or silicon germanium layers. The collector is formed as a pn-junction in a portion between the dislocation network and a surface of the silicon layer structure that is oriented away from the carrier layer, and wherein the injector is configured as a metal insulator semiconductor diode.

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract: Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.