Abstract: A board game system comprises one or more game objects, a processing device, a memory device and one or more cameras. Each of the game objects comprise a unique visual marker positioned on a top surface of the game object, wherein the unique visual marker comprises a series of concentric rings that represent data that uniquely identifies the game object. As a result, during the course of game play, the location and identification of the game objects are able to be determined by the processing device by analyzing images captured by the one or more cameras of the visual markers of the game objects on the game board. The processing device is able to compare the data of the visual markers to a table stored in the memory device that associates the data with a specific game object.

Abstract: The exemplary embodiments of the present invention include forming a photoconductor thin film on a front surface of a substrate; forming a photoconductor thin film pattern by patterning the photoconductor thin film; and forming a metal electrode on the photoconductor thin film pattern.

Abstract: A solid-state image sensor includes a pixel region and peripheral circuit region arranged on a semiconductor substrate. The pixel region includes pixels. Each pixel includes a photoelectric conversion element and an amplification MOS transistor that outputs a signal corresponding to charges of the photoelectric conversion element to a column signal line. The peripheral circuit region includes a circuit that drives the pixel or processes the signal output to the column signal line. A resistance of a source region of the amplification MOS transistor is lower than a resistance of a drain region of the amplification MOS transistor.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device has a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control electrode formed on the second insulating film. In the nonvolatile semiconductor memory device, the second insulating film has a laminated structure that has a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film, a first atom is provided at an interface between the first silicon oxide film and the first silicon nitride film, and/or at an interface between the second silicon oxide film and the first silicon nitride film, and the first atom is selected from the group consisting of aluminum, boron, and alkaline earth metals.

Abstract: A method and apparatus to test the inter-die interface between two or more semiconductor die in die stacking applications, where a mismatch exists between the number of input and output pads on a base die and the number of input and output pads on a stacked die. In a first embodiment, a number of through-die vias (TDVs) may be used to implement inter-die signal paths using standard or flexible design rules to maintain statistical TDV yield despite the lack of continuity verification of the inter-die signals paths. In alternate embodiments, programmable multiplexers may be utilized to share one or more inter-die connections between the base die and the one or more stacked die so as to facilitate testing and normal operation of each inter-die connection. In other embodiments, spare TDVs are utilized only during test operations, so as to accommodate the mismatch.

Abstract: A method and apparatus for making analog and digital electronics which includes a composite including a squishable material doped with conductive particles. A microelectromechanical systems (MEMS) device has a channel made from the composite, where the channel forms a primary conduction path for the device. Upon applied voltage, capacitive actuators squeeze the composite, causing it to become conductive. The squishable device includes a control electrode, and a composite electrically and mechanically connected to two terminal electrodes. By applying a voltage to the control electrode relative to a first terminal electrode, an electric field is developed between the control electrode and the first terminal electrode. This electric field results in an attractive force between the control electrode and the first terminal electrode, which compresses the composite and enables electric control of the electron conduction from the first terminal electrode through the channel to the second terminal electrode.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.

Abstract: A semiconductor device manufacturing apparatus includes a chamber in which a wafer is loaded; a first gas supply unit for supplying a process gas into the chamber; a gas exhaust unit for exhausting a gas from the chamber; a wafer support member on which the wafer is placed; a ring on which the wafer support member is placed; a rotation drive control unit connected to the ring to rotate the wafer; a heater disposed in the ring and comprising a heater element for heating the wafer to a predetermined temperature and including an SiC layer on at least a surface, and a heater electrode portion molded integrally with a heater element and including an SiC layer on at least a surface; and a second gas supply unit for supplying an SiC source gas into the ring.

Abstract: A semiconductor device has a buried oxide layer formed over a substrate. An active silicon layer is formed over the buried oxide layer. A drain region is formed in the active silicon layer. An LDD drift region is formed in the active silicon layer adjacent to the drain region. The drift region has a graded doping distribution. A co-implant region is formed in the active silicon. A source region is formed in the co-implant region. A shallow trench insulator is formed along a top surface of the LDD drift region. The shallow trench isolator has a length less than the LDD drift region. The shallow trench insulator terminates under the polysilicon gate and within the LDD drift region. A polysilicon gate is formed above the active silicon layer between the source region and LDD drift region and at least partially overlapping the shallow trench insulator.

Abstract: A single crystal SiC substrate is produced with low cost in which a polycrystalline SiC substrate with relatively low cost is used as a base material substrate where the single crystal SiC substrate has less strain, good crystallinity and large size. The method including a P-type ion introduction step for implanting P-type ions from a side of a surface Si layer 3 into an SOI substrate 1 in which the surface Si layer 3 and an embedded oxide layer 4 having a predetermined thickness are formed on an Si base material layer 2 to convert the embedded oxide layer 4 into a PSG layer 6 to lower a softening point, and an SiC forming step for heating the SOI substrate 1 having the PSG layer 6 formed therein in an atmosphere hydrocarbon-based gas to convert the surface Si layer 3 into SiC, and thereafter, cooling the resulting substrate to form a single crystal SiC layer 5 on a surface thereof.

Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. The increase in the numbers of gate lines and signal lines makes it difficult to mount an IC chip having a driver circuit for driving the gate line and the signal line by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit driving the pixel portion are provided over the same substrate. The pixel portion and at least a part of the driver circuit are formed using thin film transistors in each of which an oxide semiconductor is used. Both the pixel portion and the driver circuit are provided over the same substrate, whereby manufacturing costs are reduced.

Abstract: A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer.

Abstract: Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.

Abstract: According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor.

Abstract: Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.

Abstract: A thin film transistor includes a gate electrode, a first insulating layer on the gate electrode, a semiconductor layer on the gate electrode and separated from the gate electrode by the first insulating layer, the semiconductor layer including a channel region corresponding to the gate electrode, a source region, and a drain region, a hydrogen diffusion barrier layer on the semiconductor layer, the hydrogen diffusion barrier layer covering the channel region and exposing the source and drain regions, and a second insulation layer on the source and drain regions and on the hydrogen diffusion barrier layer, such that the hydrogen diffusion barrier layer is between the second insulation layer and the channel region.

Abstract: A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, a first region of a second conductivity type selectively provided in a first major surface of the semiconductor layer, a second region of the second conductivity type selectively provided in the first major surface and connected to the first region, a first electrode provided in contact with the semiconductor layer and the first region, a second electrode provided in contact with the second region, and a third electrode electrically connected to a second major surface of the semiconductor layer opposite to the first major surface.

Abstract: A light emitting diode package module structure comprises a LED module received in a reflection cup, a light transmitting color conversion member disposed on an annular surface of the reflection cup, a stationary package sleeved on the reflection cup in such a manner that the press portion of the stationary package is pressed against the light transmitting color conversion member, and the stop portions of the positioning legs of the stationary package are positioned against the bottom of the reflection cup. In this way, the light transmitting color conversion member is fixed to the reflection cup by the stationary package without the use of adhesive agents, which consequently simplifies the packaging procedure and reduces the package cost.