Abstract: A Cu interconnect having a diffusion barrier formed with the self-formed high-entropy alloy a method of preparing the same are provided. A high-entropy alloy and Cu are deposited together. When annealing, a diffusion barrier is formed through segregation of the high-entropy alloy may, toward a bottom and a sidewall of an interconnect via, and a Cu seed layer is formed through segregation of Cu at an outer surface of the diffusion barrier, so as to simultaneously self-form the diffusion barrier formed with the self-formed high-entropy alloy and the Cu seed layer. The Cu interconnect having a diffusion barrier formed with the self-formed high-entropy alloy comprises: a base, the self-formed diffusion barrier formed with the self-formed high-entropy alloy and the Cu seed layer and a Cu electroplating layer electroplating on the Cu seed layer.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: A substrate for mounting an electronic component according to an aspect of an embodiment includes a base that is a plate-shaped body, where a first surface of the base is sloped relative to a second surface that is opposed to the first surface, and when the base is bisected into a lower part and a higher part in a slope direction thereof, a thermal conductivity of the lower part is higher than a thermal conductivity of the higher part.

Abstract: A laser bonding system which improves bonding between a semiconductor chip and a substrate is provided. A laser bonding system comprises a laser bonding apparatus; and a controller configured to control the laser bonding apparatus, wherein the laser bonding apparatus includes a stage which supports a substrate including a pad, and a semiconductor chip including a connection terminal; a pressurizer which moves up and down above the stage; a temperature measuring sensor configured to measure a temperature of the semiconductor chip and generate a temperature value; and a laser radiation apparatus configured to bond a pad of the substrate and a connection terminal of the semiconductor chip, using a laser beam passing through the pressurizer, and the controller lifts the pressurizer in response to the temperature value.

Abstract: The present disclosure provides a memory structure, including a first interlayer dielectric layer (ILD), a second ILD over the first ILD, wherein at least a portion of an interconnect structure is in the second ILD, a first switch between the first ILD and the second ILD, a second switch over the first switch, and a first phase change material stacking with the first switch and the second switch.

Abstract: A self-propelled welding station including a base frame having at least one front wheel and at least two rear drive wheels, provides and independent mobility drive system with a motor and steering means for a seated or standing operator, and a utility drive system providing a self-contained, motorized welder with welding leads for remote welding and a secondary electrical generating system providing a plurality of A/C electrical outlets, an air compressor assembly to provide compressed air to operate air tools and forced air, a plurality of accessory tool and supply storage containers, accessory equipment and a bottled gas system for welding gases, gauges and hoses. The mobility drive system motor is independent from the motorized welder so that the station may be moved whether the motorized welder is on or off, and the motorized welder may be operated with the drive motor system on or off.

Abstract: A light-emitting device includes: a first light-emitting element portion including: an n-side nitride semiconductor layer, a first light-emitting layer disposed on the n-side nitride semiconductor layer, and a first p-side nitride semiconductor layer disposed on the first light-emitting layer; a second light-emitting element portion including: a second light-emitting layer disposed on the n-side nitride semiconductor layer, and a second p-side nitride semiconductor layer disposed on the second light-emitting layer; an n-side electrode connected to the n-side nitride semiconductor layer; a first p-side electrode disposed on the first p-side nitride semiconductor layer via an upper n-type semiconductor layer disposed on the first p-side semiconductor layer; and a second p-side electrode connected to the second p-side nitride semiconductor layer. A composition of the second light-emitting layer is different from a composition of the first light-emitting layer.

Abstract: A semiconductor device includes a semiconductor element, a first terminal, a second terminal, a first conductor, a first connecting member, and a second connecting member. The semiconductor element includes a first electrode, a second electrode, and a third electrode, and is configured to perform on/off control between the first electrode and the second electrode based on a drive signal inputted to the third electrode. The first terminal and the second terminal are separated apart from each other and electrically connected to the first electrode. The first conductor is electrically connected to the first terminal. The first connecting member electrically connects the first electrode and the first conductor. The second connecting member electrically connects the first conductor and the second terminal.

Abstract: A semiconductor device includes a heat dissipation member, multiple switching elements, and multiple signal terminals. The switching elements include a first switching element formed on a silicon substrate and a second switching element formed on a silicon carbide substrate, and include at least one of the first switching element or the second switching element in a plural number Each of the switching elements includes a temperature sense pad. The first switching element and the second switching element are alternately arranged in a predetermined direction in which a refrigerant flows. In the switching elements of same type as the switching element disposed on a most downstream side in the predetermined direction, the signal terminal corresponding to the temperature sense pad is provided for the switching element disposed on the most downstream side, and is not provided for the switching elements disposed on more upstream side.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

Abstract: Methods for forming a semiconductor device are disclosed. According to some aspects, a first implantation is performed on a first of a first semiconductor structure to form a buried stop layer in the first substrate. A second semiconductor device is formed. The first semiconductor structure and the second semiconductor device are bonded. The first substrate is thinned and the buried stop layer is removed, and an interconnect layer is formed above the thinned first substrate.

Abstract: Multi-operation tools for photovoltaic cell processing are described. In an example, a multi-operation tool includes a conveyor system to move a photovoltaic (PV) cell continuously along a conveyor path through a laser scribing station and an adhesive printing station. Furthermore, the PV cell may be aligned to a laser head of the laser scribing station and a printer head of the adhesive printing station in a single alignment operation prior to being laser scribed and printed with an adhesive in a continuous process.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Abstract: A semiconductor device includes: a bit line structure formed over a substrate; a storage node contact plug spaced apart from the bit line structure; and a nitride spacer positioned between the bit line structure and the storage node contact plug, wherein the nitride spacer has a higher silicon content in a portion adjacent to the storage node contact plug than in a portion adjacent to the bit line structure.

Abstract: An electric heater (1, 1?) for heating a substance inside a tank (100), the electric heater (1, 1?) comprising: —at least one resistive wire (4) adapted to be connected to a source of electricity, said at least one resistive wire (4) being provided with a sheath (41) made of electrically insulating material; —at least a first thermally conductive sheet (5) made of metal fixed to the at least one resistive wire (4); —at least two protective layers (2, 3) made of polymer material, fixed to each other; wherein the at least one resistive wire (4) and the at least a first sheet (5) are arranged between the at least two protective layers (2, 3).

Abstract: Embodiments of the present application provide a semiconductor structure formation method and a semiconductor structure. The method includes: the substrate including contact region and dummy region, a first bitline structure and a first dielectric layer being formed on the substrate, the first bitline structure and the first dielectric layer defining discrete capacitor contact openings; forming a first sacrificial layer filling the capacitor contact opening; removing, in the dummy region, part of height of the first bitline structure, part of height of the first dielectric layer and part of height of the first sacrificial layer to form a first opening located at top of a second bitline structure, a second dielectric layer and a second sacrificial layer; forming an insulation layer filling the first opening; removing, in the contact region, the first sacrificial layer to form a second opening; and forming a capacitor contact structure located in the second opening.

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.