Abstract: A semiconductor structure includes a substrate having first and second bottom electrodes disposed thereon. The first bottom electrode includes a first sidewall and a second sidewall. An upper portion of the first sidewall comprises a slope profile. The second bottom electrode includes a third sidewall and a fourth sidewall. The second sidewall is opposite to the third sidewall. An upper supporting layer extends laterally between and the first bottom electrode and the second bottom electrode and directly contacts the second sidewall and the third sidewall. A lower end of the slope profile is not lower than a lower surface of the upper supporting layer. A cavity extends laterally between the substrate and the upper supporting layer. A capacitor dielectric layer is formed along the first bottom electrode and the second bottom electrode. A conductive material is formed on the capacitor dielectric layer and fills the cavity.

Abstract: A manufacturing method of a semiconductor device includes sealing a metal plate on which a semiconductor chip and a control IC are mounted by injecting molding resin raw material into a cavity from an inlet, filling the cavity with the molding resin raw material, and discharging excessive molding resin raw material from an outlet. In the case of the semiconductor device manufactured in this way, at least, generation of voids is reduced in an area around the semiconductor chip and the control IC. Thus, occurrence of an electrical discharge in the semiconductor device is reduced, and deterioration of the reliability of the semiconductor device is prevented.

Abstract: A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.

Abstract: The embodiments disclosed in this document are directed to an AI-enabled microgrid and DER planning platform that uses AI methods and takes into account cost calculations, emission calculations, technology investments and operation. In an embodiment, the computing platform is deployed on a network (cloud computing platform) that can be accessed by a variety of stakeholders (e.g., investors, technology vendors, energy providers, regulatory authorities). In an embodiment, the planning platform implements machine learning (e.g., neural networks) to estimate various planning parameters, where the neural networks are trained on observed data from real-world microgrid/minigrid and DER projects.

Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.

Abstract: Provided are a III-nitride semiconductor light-emitting device that can reduce change in the light output power with time and has more excellent light output power, and a method of producing the same. A III-nitride semiconductor light-emitting device 100 has an emission wavelength of 200 nm to 350 nm, and includes an n-type layer 30, a light emitting layer 40, an electron blocking layer 60, and a p-type contact layer 70 in this order. The electron blocking layer 60 has a co-doped region layer 60c, the p-type contact layer 60 is made of p-type AlxGa1-xN (0?x?0.1), and the p-type contact layer 60 has a thickness of 300 nm or more.

Abstract: Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70° C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Abstract: A light emitting device includes a substrate, a plurality of light sources disposed on the substrate, and a plurality of light reflecting members disposed on the substrate. The light reflecting members respectively include wall parts each surrounding each of the light sources individually or two or more of the light sources in groups. Two adjacent ones of the light reflecting members are joined to each other such that outer surfaces of the wall parts of the two adjacent ones of the light reflecting members are bonded to each other via an adhesive agent.

Abstract: A polishing slurry including a hydrophilic nanocarbon particle having a nitrogen-containing functional group, and a weight ratio of a nitrogen element relative to a carbon element of the hydrophilic nanocarbon particle, the weight ratio expressed as N/C×100% is greater than or equal to about 5 wt %, and a method of manufacturing a semiconductor device using the polishing slurry.

Abstract: Embodiments of the present disclosure provide a memory and its manufacturing method. The memory includes: a substrate with a plurality of mutually discrete bitlines, the bitline including a bitline conductive layer and a bitline insulating layer which are stacked in sequence; and an insulating layer and capacitor contact holes, the insulating layer being located on sidewalls of the bitline conductive layers and sidewalls of the bitline insulating layers, the capacitor contact holes being located between adjacent ones of the bitline conductive layers, sidewalls of the capacitor contact holes exposing the insulating layer, an opening size of the capacitor contact hole gradually increasing in a direction along the substrate and towards the insulating layer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

Abstract: An integrated circuit (IC) is provided that includes a plurality of physical unclonable function (PUF) structures located in a PUF area. Each PUF structure of the plurality of PUF structures includes at least a PUF top electrically conductive structure containing random sidewall voids and random line openings which can provide an encrypted security code to the IC. The IC further includes a plurality of memory structures located in a memory area that is located laterally adjacent to the PUF area. Each memory structure of the plurality of memory structures includes a memory element sandwiched between a bottom electrically conductive structure and a top electrically conductive structure. The top electrically conductive structures are devoid of sidewall voids and line openings.

Abstract: Stack assembly for radio-frequency applications. In some embodiments, a radio-frequency (RF) module can include a packaging substrate configured to receive a plurality of components, and an electro-acoustic device mounted on the packaging substrate. The RF module can further include a die having an integrated circuit and mounted over the electro-acoustic device to form a stack assembly. The electro-acoustic device can be, for example, a filter device such as a surface acoustic wave filter. The die can be, for example an amplifier die such as a low-noise amplifier implemented on a silicon die.

Abstract: A system and method for multi-agent reinforcement learning in a multi-agent environment that include receiving data associated with the multi-agent environment in which an ego agent and a target agent are traveling. The system and method also include learning single agent policies that are respectively associated with the ego agent and the target agent based on the data associated with the multi-agent environment. The system and method additionally include learning a multi-agent policy as an interactive policy that enables the ego agent and the target agent to account for one another while traveling to respective goals within the multi-agent environment based on the single agent policies. The system and method further include implementing the multi-agent policy to control at least one of: the ego agent and the target agent to operate within the multi-agent environment.

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

Abstract: This invention provides a temperature sensor circuit and its operation method. The temperature sensor circuit includes a temperature sensor, a temperature comparator, a plurality of temperature sensor enable clocks with different clock cycles and a clock selection circuit. The temperature sensor detects a temperature of an Integrated circuit and sending a signal indicative of the temperature. The temperature comparator executes a comparison between the temperature of the Integrated circuit and a predetermined temperature setting upon receiving the signal indicative of the temperature and sending an output according to the comparison. Upon receiving the output, the clock selection circuit provides one of the temperature sensor enable clocks according to the output to enable the temperature sensor. The temperature detection cycle of the temperature sensor is thus adjustable to save the temperature sensor power.

Abstract: Embodiments disclose a capacitor array structure and a method for fabricating a capacitor array structure. The method includes: after forming a first capacitor hole, providing a bonded wafer including a second substrate, a second supporting layer and a second sacrificial layer stacked in sequence, and bonding the bonded wafer to a stacked structure, wherein a surface of the second sacrificial layer away from the second supporting layer is a bonding surface; forming a second capacitor hole, the second capacitor hole penetrating into the bonded wafer at least along a thickness direction to expose the first capacitor hole, such that the first capacitor hole is connected with the second capacitor hole.

Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.

Abstract: A display panel and an organic light emitting display device with enhanced light extraction efficiency is described. The display panel and the display device include an insulating film including at least one concave portion, a first electrode disposed to cover the concave portion, a bank including a first part on the first electrode and overlapping a part of the flat portion of the concave portion, a second part extending from the first part and overlapping an inclined portion of the concave portion, and a third part extending from the second part and disposed on the side portion, an organic layer overlapping the concave portion, and a second electrode on the organic layer and the bank. A width of the first part of the bank is wider than a width of the second part of the bank. Thus, it is possible to provide a display device with enhanced light extraction efficiency.