Abstract: A host interface 1 for an asynchronous transfer mode (ATM) network comprises a Segmenter 2 and Reassembler 3. The host interface 1 is connected to a Sunshine ATM switch 7 via an electrical to optical converter 6 and an IBM RS/6000 workstation 4 via a MicroChannel bus 5. The Reassembler 3 comprises three components, respectively referred to as the Linked List Manager, Dual Port Reassembly Buffer and SONET Interface and VCI Lookup Controller, that are capable of concurrent operation once they are initialized and configured. Those components are capable of reassembling an ATM cell in less than 2.7 microseconds.

Abstract: In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit.

Abstract: A method and apparatus for processing a reconstructed speech signal from an analysis-by-synthesis decoder are provided to improve the quality of reconstructed speech. By operation of the invention, one or more traces in a reconstructed speech signal are identified. Traces are sequences of like-features in the reconstructed speech signal. The like-features are identified by time-distance data received from the long term predictor of the decoder. The identified traces are smoothed by one of the known smoothing techniques. A smoothed version of the reconstructed speech signal is formed by combining one or more of the smoothed traces. The original reconstructed speech signal may be that provided by a long term predictor of the decoder. Values of the reconstructed speech signal and smoothed speech signal may be combined based on a measure of periodicity in speech.

Abstract: Method and apparatus for a demand scheduled partial carrier load planning system for the transportation industry, designed to distribute planned and random orders, each order having a source point and a destination point in the territory served, and for distributing products and materials in a predetermined geographic territory, primarily intended for use in connection with wheeled vehicles traveling over public highways.

Abstract: A parallel computer comprising a plurality of processors and an interconnection network for transferring messages among the processors. At least one of the processors, as a source processor, generates messages, each including an address defining a path through the interconnection network from the source processor to one or more of the processors which are to receive the message as destination processors. The interconnection network establishes, in response to a message from the source processor, a path in accordance with the address from the source processor in a downstream direction to the destination processors thereby to facilitate transfer of the message to the destination processors. Each destination processor generates response indicia in response to a message. The interconnection network receives the response indicia from the destination processor(s) and generates, in response, consolidated response indicia which it transfers in an upstream direction to the source processor.

Abstract: An integrated hardware multiprocess scheduler for controlling a plurality of concurrently operating graphics generating subsystems required for the generation of display signals for a graphics rendering processor. In so doing, the hardware scheduler controls the operations of these subsystems in parallel, while incorporating in hardware, certain aspects of a software operating system. This feature promotes functional independence between the various controlled subsystems and promotes communication between them. Such independence is accomplished by the structure of the scheduler which is set up so that each of the controlled subsystems is connected to a common status/enable bus in parallel with the other controlled subsystems and each of them is operationally independent of the others. Depending on the instructions received, the scheduler enables and disables one or more of these subsystems at essentially the same time.

Abstract: A print control apparatus for controlling a page printer, such as a laser printer. The print control apparatus comprises a plurality of page buffers provided in units each corresponding to a page having a minimal or relatively small paper sheet size. A necessary numbers of page buffers are acquired and then released by a draw task or a print task according to the page size to be printed so that printing can be carried out even on large size paper sheets with less total capacity of the page buffers and printing can be carried out on average at the highest speed of the printer engine on small size paper sheets even if there is a page containing a lot of drawing data during a continuous printing operation.

Abstract: An office communication system for transmitting data and/or video information through a communication network to a given device and at a given point in time. An automatic selection device is provided having a timer circuit with a calendar function which may be adjusted by the user along with control device. The automatic selecting device makes a connection through the communication network corresponding to the time desired by the user. A data transmission occurs through a communication interface means at a time which is cost favorable to the user.

Abstract: A selectible computer tape drive activation and deactivation technique apparatus is disclosed. The invention integrates with existing floppy controllers in a manner which allows activation and deactivation of a computer tape drive without the need for select lines. The invention programs the floppy controller so as to generate an activation command which may be appended by an address to specify the specific drive involved. Both the command and the argument are chosen to be consistent with existing Quarter Inch Committee standards. With respect to the deselect method, additionally a failsafe, independent deactivation path exists to turn off the tape drive in the event any conflict in drive operations were to exist.

Abstract: A method and apparatus which eliminates beat like artifacts that occur when an RF signal is mixed with a pulsed signal of similar, but not identical, frequency to the RF signal. A controller for synchronizing the phase of a RF carrier signal to a video signal provides beat elimination in a high pixel rate laser printer. The video signal and RF carrier signal are multiplied and sent to an acousto-optic modulator for pulsing a uniform burst of energy in the form of a laser beam to a photoconductor. The controller may include a synchronous gateable crystal oscillator with logic such as TTL, CMOS, ECL or equivalent logic functions using discrete transistors, where the synchronous gateable crystal oscillator is frequency dependent upon a laser printing speed. Eliminating imaging defects such as variable pixel width and density provides a sharper, uniform pixel printout.

Abstract: An electronically programmable read-only memory module has an embedded micro-controller for program/data updating.Upon power up, the module acts as a prior art ROM. The embedded micro-controller in a standby mode is responsive to data arriving from a download communication interface that is accessible by an external port on the module. The external port and download communication interface is independent of the system of which the module is an operating component. When a command is received from the download communication interface, the micro-controller switches the memory device to respond to micro-controller inputs that starts an update session. The micro-controller receives download data from the download communication interface and writes it into the memory device. When the download process terminates, the micro-controller switches the memory device back to its system interface.

Abstract: A data transfer system for transferring data among plural terminals which are connected through a transmission line. each terminal capable of performing distributed processing and includes an unit for delivering on the line a first signal having an identification information of a user who utilizes the terminal and an identification information of the terminal and a unit for delivering on the line a second signal having an identification information of a destination user to which data is to be transferred as an identification information of the terminal which is a delivery source of the data.

Abstract: A computing system (50) includes N number of symmetrical computing engines having N number of cache memories joined by a system bus (12). The computing system includes a global run queue (54), an FPA global run queue, and N number of affinity run queues (58). Each engine is associated with one affinity run queue, which includes multiple slots. When a process first becomes runnable, it is typically attached one of the global run queues. A scheduler allocates engines to processes and schedules the processes to run on the basis of priority and engine availability. An engine typically stops running a process before it is complete. When the process becomes runnable again the scheduler estimates the remaining cache context for the process in the cache of the engine. The scheduler uses the estimated amount of cache context in deciding in which run queue a process is to be enqueued.

Abstract: An input/output control apparatus connected to a plurality of input/output units such as disc systems and an input/output control method. A cache memory is divided into a plurality of storage areas for data management. Data stored in the disc systems are stored in the storage areas. In response to an output request from a HOST system to the disc systems, data outputted from the latter are stored in the storage areas of the cache memory. The data stored in the storage areas and outputted therefrom in response to the output request are transferred to the disc systems. The storage areas storing the data requested and not yet stored in the disc systems are grouped correspondingly to the disc systems where the output data are to be stored. The resulting group is managed as a first attribute group. Write-after processing for every disc units can be executed in parallel efficiently without involving high processing overhead.

Abstract: An interface between a real-time data link and a digital computer system utilizes data buffers between the computer central data storage and the data link. An interface control processor is responsive to a Data Transfer Command set comprising a SEND, a GET, a SET-TAG and a TERMINATE command. The commands include a TAG parameter that is set by the SET-TAG command to group sequences of SEND and GET commands so that logical streams of data are continuously transmitted and received across the interface. The SEND command includes a RECEIVE parameter to initiate the transfer of received data from the data link to the buffers after all data associated with the SEND command has been transmitted. Data transmission and reception operations are terminated by a TERMINATE command with a TAG parameter matching the TAG parameters of the sequence of commands controlling the operations. The SEND, GET and SET-TAG commands are stacked in a command queue and applied sequentially to the control processor.

Abstract: An address processing unit for use in a graphics controller is disclosed. The address processing means performs a variety of address processing functions including conversion between two-dimensional and linear addresses.

Abstract: An improved system for recording and playing back digital information in a special pulse-length modulation format on a disc-shaped record. The digital information is stored in a succession of alternating marks and spaces, both having lengths that are discretely variable in accordance with a succession of multi-bit binary code blocks.

Abstract: An improved method and apparatus for downloading compressed audio/visual (AV) data and/or graphical/tabular information from a remote Server to an End User Station (EUS) for the purpose of decompressing and/or displaying said downloaded data. The EUS may transmit a query to the Server manually and/or automatically for the purpose of initiating a process in the Server (e.g. data compression, indexing into a very large database, etc.), which requires the high speed processing, large capacity and multi-distributed data storage, etc.) which are typically preferred at a Server. The EUS provides appropriate inverse processing (e.g. data decompression) which, by its nature, requires relatively little processing power to accomplish. Thus, the method of this invention exploits the inherent asymmetry in the overall process of an EUS querying a remote Server (and/or Server Network) for a data service (e.g.

Abstract: A pixel color processor that performs supplemental graphical processing duties in a video unit in a computer system. The pixel color processor is interfaced between a processor and video memory and performs pixel string manipulation and color management duties on the pixel color data at the direction of the processor, thereby freeing up the processor of these duties. The memory address space of the processor includes a monochrome memory area which maps onto the full-depth packed-pixel video memory. When the processor performs operations on this monochrome area, the pixel color processor intercepts the addresses data generated by the processor and performs the pixel block transfers.

Abstract: The invention provides a data processing network having a first processor, a second processor and a communication system linking said first processor and said second processor characterized in that when said first processor issues a call for triggering said second processor to allocate a real identifier for an entity, control logic associated with said first processor and responsive to said call from said first processor allocates a local identifier available for immediate use by said first processor and subsequently transforms between said local identifier and said real identifier. The invention both recognizes and solves the problem of a first processor being delayed while waiting for an identifier to be supplied by a second processor. Control logic associated with the first processor provides a local identifier for use by the first processor without having to wait for the real identifier from the second processor.