Abstract: A still video apparatus in which a picture of an object and a sound recorded on a recording medium as an electrical picture signal and sound signal are reproduced. The still video apparatus includes a picture reproducing device which reproduces the picture signal and the sound signal recorded on the recording medium, a picture fading device which fades the picture signal reproduced by the picture reproducing device, and a sound fading device which fades the sound signal reproduced by the picture reproducing device.

Abstract: An installation creates a source I/O definition file (IODF), defining a current system I/O configuration, and a target IODF, defining a future I/O configuration. When the configuration definition is dynamically changed from the current to the target, a serialization mechanism--comprising a "device pin" technique and a "group serialization" technique to handle changed device group definitions--insures that data integrity is not lost on devices undergoing reconfiguration; and a change detection mechanism insures that changes to control structures affected by the dynamic reconfiguration, are noticed by programs accessing those control structures while the structures are changing.

Abstract: A method is provided for decreasing the power consumption of a sequential digital circuit having a plurality of states being determined from the current state and the input conditions and entered upon the assertion of a pulse from one or more clocks. The method consists of interrupting the switching created by the clock pulses and maintaining the system in a quiescent state. It is first determined whether a subsequent clock pulse will lead to a change in the state of the circuit. If it will, the circuit either waits for a change in the input conditions and state of the circuit, or changes some of the input conditions, depending on the embodiment of the invention. When a circuit configuration is reached in which further clock pulses will not lead to a change in the state of the circuit, the clock signal(s) are replaced by continuously asserted signals. The feedback loop thus created maintains the current state of the circuit in the absence of a clock signal and prevents further switching in the circuit.

Abstract: A parallel data processing apparatus including a plurality of processors, a pair of signal paths are provided for each processor, one signal path of each pair being used for supplying a predetermined signal to the processor, and the second signal path being used for returning the signal from the processor to a predetermined position common to all of the processors. Each of the above signal paths include a variable delay unit. The apparatus further includes a delay measuring unit for measuring the time elapsing while the signal is propagated from the above predetermined position to a corresponding processor and then returned from the processor to the above predetermined position through each pair of signal paths. Further the apparatus includes a delay adjusting unit for adjusting the delays caused by the variable delay units in all of the signal paths.

Abstract: A signal recording apparatus for recording a TV signal in which an audio signal such as a MUSE signal and a video signal are multiplexed in a time sharing manner in units of a given period of time, is arranged to code these video and audio signals alike, to dispersively allocate a discretely separated audio signal within the video signal, to provide symbols other than the symbols of the audio and video signals within each synchronizing block for the purpose of permitting the use of other video signal recording apparatuses. The arrangement permits simplification and high-quality of the apparatus for recording the signals of this kind and thus contributes to the popularization of the apparatus.

Abstract: A programmable controller with an I/O signal converting circuit having an input element and an output element, comprises a signal I/O unit having a plurality of element sockets capable of replaceably accommodating both the input element and the output element; a selecting unit for selecting the type of the accommodated element; and a signal storing and sending unit. Each element socket may accommodate the input and output elements. Therefore, the space required to install the I/O circuits is reduced, and the number of input and output elements can be arbitrarily set.

Abstract: A paging receiver has a predetermined minimum operating voltage. A method of operation thereof comprises the step of determining the predetermined minimum operating voltage of the paging receiver operating the paging receiver at a plurality of different operating voltages until the paging receiver operates unsatisfactorily, and selecting the operating voltage of the paging receiver at a level greater than the unsatisfactory operating voltage.

Abstract: A dual selection system for a reference frequency for use in a clock comprising a microcomputer for controlling the whole system and outputting a switching signal and frequency-demultiplying signals. A system oscillator produces an oscillation signal of 4.194304 MHz. A system frequency-demultiplier for frequency-dividing an output of a first buffer to apply a system clock signal to the microcomputer. A clock oscillator produces an oscillation signal of 32.768 KHz, and a clock frequency-demultiplier for frequency-dividing an output of a second buffer applies a clock signal of 1 Hz for clock to the microcomputer.When an option is selected, a system oscillation signal of 4.194304 MHz is selected and frequency-demultiplied by 2.sup.22 to a clock signal of 1 Hz for a clock. When that the option is not selected, the clock oscillation signal of 32.768 KHz is frequency-divided by 2.sup.15 to a clock signal of 1 Hz for the clock.

Abstract: Apparatus and method for transferring segmented memory between memory units determines a need for memory transfer and searches a memory unit segment by segment until a valid data record is found. This valid data record is conveyed to another memory unit via the asynchronous mode. If a valid data records is not found within a predetermined amount of time, a message identifying the memory segment last searched is conveyed. If no remaining valid data records are found, a message with no information is conveyed. Priority is given to asynchronous messages.

Abstract: A multiprocessor having a plurality of processor elements connected in a cascaded manner. A memory is shared between each processor element and a processor adjacent in an upper or lower rank to the processor. In the lower processor element, there are disposed an arbiter for arbitrating a memory access with its upper processor element and a bus selector for switching a bus with the arbiter. The processor elements are connected in a multistage tree structure by a bus connection only. From the upper processor element, therefore, there can be accessed the shared memory in the lower processor element only through an external bus. The whole system is not limited by the address space of each processor and the bus, even if the address space is finite, so that the real memory capacity can be limitlessly expanded in a manner to correspond to the internal memory of each processor element.

Abstract: In a memory device shared among processors, a communication buffer having a size requested by the processing program of the origin of sending is dynamically secured. After the communication buffer has been secured, the send program writes a message to be conveyed to the receive program into the above described communication buffer and asks the send OS to perform sending. The send OS sends a communication ID having "1" set in the bit position corresponding to the receive program. On the basis of the above described bit position, the receive OS specifies a receive program and informs the receive program of that fact. The receive program reads a message from the communication buffer. Communication between the send program and the receive program is thus realized. A send instruction and a receive instruction respectively for exclusive use of sending and reading out a communication ID are prepared beforehand.

Abstract: An optical disc for a sample servo type optical disc system. Servo areas disposed periodically on each of tracks of the optical disc are sequentially offset relative to those on the adjacent tracks as viewed in the radial direction by a predetermined distance. An apparatus used for signal read-out from the optical disc comprises a circuit for detecting a servo signal originating in servo pits from a detection signal output from a photodetector, a circuit for generating a clock signal synchronized with the servo signal, a counter for outputting a count value representative of the counted clocks at the timing of the servo signal, and a circuit for generating a light spot velocity signal from the count value.

Abstract: A secondary cache control system for a computer system is disclosed. The system is utilized advantageously to reduce the cost of the SRAM while not degrading the overall performance of the CPU associated with the computer. The system latches the data from the CPU until the CPU hits a "dead time". When this dead time occurs, the data is written into the SRAM. By writing to the SRAM at this time the performance of the computer system is not degraded and the cost of the SRAM is significantly reduced.

Abstract: An apparatus which inspects disc-shaped information recording media, such as optical disks and magnetic disks, in a single reproduction. The apparatus detects the type of defect and classifies the defects into defect clusters by the defect position in the radial and circumferential directions. Type of defect or defect cluster, position and size are memorized.

Abstract: An apparatus and method for operating a system component in a microprocessor system. The component is operated by a component controller which runs off a clock having a frequency different than the system clock. The controller is synchronized with the system clock at the conclusion of a component access cycle. The state machine of the controller can thus operate independently of the system clock and timing options implemented by the controller need not have an even number of states.

Abstract: There is disclosed a data processing apparatus in which when a data existence position pulse indicative of the input of a data signal is supplied, a process of the supplied data signal is started in response to the leading edge of the data existence position pulse, a pulse signal of a predetermined width is generated after the elapse of only a first predetermined time from the leading edge of the data existence position pulse, the generation of an output data signal indicative of the result of the process is blocked by a switch for the generating period of the pulse signal, and the output data signal indicative of the result of the process is relayed and transmitted by the switch for only a second predetermined time from the extinguishment of the pulse signal. Thus, only the effective data can be generated.

Abstract: This invention relates to a tape drive with an electronic buffer which temporarily stores data transferred between the host computer and the tape drive's magnetic tape. More specifically, during a write transaction, in which data is transferred by the host computer to the tape drive for storage, the present invention involves the buffer having an adjustable threshold, or "watermark", which must be reached by the data stored in the buffer before the tape drive begins the operation of ramping the tape up to its write velocity so that it can record the data stored in the buffer. To the extent that the rate at which data is sent to the tape drive from the host computer may vary, the adjustment of the watermark by the tape drive is for the purpose of locating the watermark that is optimal for the data input rate at any given point in time. It does so with its chief objective being the maximization of the tape drives availability to accept data from the host computer whenever the host is ready to send data.

Abstract: A data communication apparatus includes a command receiving unit for receiving a command for setting up a call; a discriminating unit for discriminating a bearer capability included in the command received by the command receiving unit; and a judging unit for judging if a modem is to be used or not, in accordance with a discrimination result by the discriminating unit.

Abstract: A method and apparatus are provided for enabling a computer that is capable of running programs utilizing different address sizes to run those programs without having to modify the computer's hardware. A mask register is used to identify bits of a sum of register addresses that are valid for the program that is running. The number of valid bits in the register mask can be changed to correspond to the addressable memory size for different programs.

Abstract: A method of dynamically reconfiguring a UART polling loop with a jump table.