Abstract: A communication network system comprising a communication line network, a plurality of terminals connected to the communication line network, and a fuzzy control unit for allocating a right to access the communication network according to a fuzzy deduction process taking into account an operating condition of the system. This communication network system may consist of a local area network involving a polling process or a token passing process, a computer terminals systems, or a telephone exchange system. By using a fuzzy control process, an efficient utilization of available resources is made possible by taking into account operating conditions of the network as a whole, or each of the terminals.

Abstract: A power-switching device (such as a gate-controlled TRIAC) is used to connect and disconnect a computer system's power supply unit from the power-line connection. This power-switching device is controlled by a battery-powered circuit. The battery-powered circuit monitors a contact pad, and powers up the system when the user touches the contact. Thus, when the system is powered down, all parts of the system are disconnected from AC power.

Abstract: The present invention works in combination with an integrated set of hardware and software tools that support rapid design, programming, debugging, implementation, and testing of local operation network local operation network nodes and applications. These hardware and software tools speed development by enabling developers to use object-oriented concepts, such as network variables and input/output objects, rather than low-level constructs. The development environment operates with an IBM PC/AT or compatible computer and can grow from a single emulated application node to a completely distributed system of up to 24 emulated nodes and hundreds of remote nodes. The invention is mainly directed to a repeater circuit which is part of a control processor board, and is used to send and receive the serial signals between the PC and connected development stations, and the serial data protocol which enables the development stations to be automatically configured at system start-up.

Abstract: A data flow control system for regulating the flow of data through a buffer memory in a data storage system controller. The data flow controller system includes an up-down counter that is decremented for every byte of data that is placed into the controller's buffer memory, and incremented for every byte of data that is taken out of the buffer memory. The counter is preset to an initial value that represents the minimum amount of data that must be in the buffer memory before that data can be released to the storage system or to the computer interface, thereby permitting validation of the data prior to release. The value of the counter represents the amount of data that is in the buffer memory less the initial offset value. Detector circuitry coupled to the counter enables or disables the storage system or the computer interface depending upon the validity of the data in the buffer memory and the operational status of the storage system and the computer interface.

Abstract: A system including a plurality of terminal apparatuses connected to each other via a communication network for achieving joint information processing, such as involved in an electronic joint project and an electronic meeting. The terminal apparatuses are interconnected to each other via a logical ring path formed on the communication network. Each terminal apparatus is loaded with a control program for supervising the joint information processing. Each control program functions in cooperation with control programs of other terminal apparatuses to conduct communication procedures for establishing, for changing, or for terminating the logical ring path and to control a display operation to supply the user with information identifying those members currently participating in the joint information processing.

Abstract: A method and apparatus for distributing the processing of certain remote terminal keystroke signals, and formatting of display panels according to user interface rules, to a workstation control interface in a system having a host processor connected to a large number of remote keyboard/display terminals through an intermediate workstation control interface.

Abstract: In a computer system having both peripherals having their own DMA channel arbiter and peripherals having no arbiter, a separate arbitration unit, controlled directly by the CPU, is provided to arbitrate on behalf of peripherals having no arbiter. The CPU can thus freely assign different arbitration levels to such peripherals, and can instruct the arbitration unit to simultaneously arbitrate on different arbitration levels or for two or more DMA channels.

Abstract: A parallel interface connects a data processor and a printer so that each may transmit information to the other or receive information from the other. The transmitted information from the data processor can be data or status signals. The data or status signals are transmitted over the same eight information lines between the data processor and the printer with a predetermined signal being sent over another line from the data processor to the printer prior to transmission over the eight lines to identify whether the transmitted information is data or status signals. The printer sends status signals to the data processor over the same eight information lines after sending a predetermined signal to the data processor over a further line that it is going to transmit.

Abstract: A gateway device for connecting a computer bus to a high-speed fiber optic ring network including an I/O host module of the computer connected to the computer bus and having at least one external communication bus for carrying both data and control blocks containing parameters relative to the composition of data frames. The gateway device also includes an adapter device physically connected to the network, and an interface which ensures transfer of the data and control blocks between the I/O host module and the adapter device. The adapter device includes a memory for storing the data frames before they are transmitted to the network and after they are received from the network, and a transfer management controller for managing the transfer of data frames between the I/O host module and the network. The controller includes a control bus which carries the control blocks and the control characters of the data frames. The adapter device further includes a high-speed bus which transports the data.

Abstract: In a data processing system a structure (50) called an I/O association is constructed. An I/O association (50) is a symmetric structure which allows not only consumer (52) of a service to locate the provider (54) of the service, but it also permits the converse. In some respects, an I/O channel (32) is only half of an association (50). The association (50) describes a targeted object (56) and provides the means (57) of locating the necessary procedures to operate on the target (56). The association (50) also describes a source object (58) that is held responsible for the requested operation, as well as the means (60) of locating and invoking procedures to report results to the source object (58).

Abstract: A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

Abstract: A system for creating a program for a programmable logic controller (PLC). The user inputs a ladder logic command in an alphanumeric format, and the system creates a corresponding ladder logic graph on a display means. The user may then verify the relationship depicted in the graph, before forwarding the ladder logic command to the PLC.

Abstract: The device serves to adapt a printer to an autonomous facsimile transmission apparatus. It comprises line interface for transmitting and receiving data conveyed via a telephone line; a printing interface; an input interface for entering data derived from at least one external digital device; a coder/decoder connected to the line interface for respectively encoding and decoding data derived respectively from the input interface and from the line interface. Data derived from the input interface either towards the line interface is routed via the coder/encoder or towards the printing interface. Data derived from the line interface is routed towards the printing interface.

Abstract: An original image signal is encoded into an image code signal of a predetermined format through an approximation process on colors. A first luminance component is derived from the image code signal. A second luminance component is derived from the original image signal. A difference between the first luminance component and the second luminance component is derived. The difference is converted into a luminance corrective signal. The image code signal and the luminance corrective signal are transmitted via a common transmission line. In a decoder, the luminance corrective signal is decoded to a luminance difference signal, which is added to an image signal decoded from the image code signal.

Abstract: A synchronized phase adjustment system provides relative synchronization of the clock oscillators in a mesh-connected parallel processor. Each node of a mesh contains an independent voltage controlled oscillator, and each node is linked to adjacent nodes by phase detectors. The phase differences between a node oscillator and the oscillators of adjacent nodes are combined by an input circuit the output of which is an average value applied to the node oscillator. The transfer function of the signal input to an oscillator relative to detected phase error indicates the restoring force (voltage) which is provided to adjust the phase of that oscillator. It is shown that a stable latch-up state in which all node phases of a mesh are not equal requires that one of the phase differences between two nodes is greater than .pi./2. Thus, the transfer function of the signal input to an oscillator is given a negative slope for phase differences having an absolute value between .pi./2 and .pi..

Abstract: A method and system for displaying a function in two dimensions where the function is made up of numerous independent variables and at least one dependent variable. A new independent variable value can be defined having values which correspond to the multiple dependent variables. The variable values are read into a computer and the independent variables are then ranked by the user from fastest- to slowest-running variable. Each dependent variable corresponding to the new independent variable is plotted along the Y-axis. The independent variable values are plotted along the X-axis in a hierarchical manner. The hierarchical manner involves a nesting of fastest-running variables within slower-running variables. Rectangles are then drawn to correspond to each variable value. Each rectangle horizontally encloses the faster-running variables associated with it.

Abstract: The redundancy contained within the spectral amplitudes is reduced, and as a result the quantization of the spectral amplitudes is improved. The prediction of the spectral amplitudes of the current segment from the spectral amplitudes of the previous is adjusted to account for any change in the fundamental frequency between the two segments. The spectral amplitudes prediction residuals are divided into a fixed number of blocks each containing approximately the same number of elements. A prediction residual block average (PRBA) vector is formed; each element of the PRBA is equal to the average of the prediction residuals within one of the blocks. The PRBA vector is vector quantized, or it is transformed with a Discrete Cosine Transform (DCT) and scalar quantized. The perceived effect of bit errors is reduced by smoothing the voiced/unvoiced decisions. An estimate of the error rate is made by locally averaging the number of correctable bit errors within each segment.

Abstract: There is disclosed a switch matrix and operational method relying upon a high degree of operational logic at each matrix crosspoint. In one embodiment, the switch is used in a multiprocessor system arranged as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. The switch matrix serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories and is contained on a single silicon substrate.

Abstract: A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

Abstract: A high performance communications interface device for connecting a high speed computer to a high performance communications bus. The high performance communications interface device includes a high performance communications interface device processor, a source interface, a destination interface and at least one I/O processor which controls the transfer of data to the high speed computer from the high performance communications bus and from the high speed computer to the high performance communications bus.