Abstract: A CMP slurry composition for copper films and a method of polishing a copper film using the same are disclosed, the composition including a polar solvent or a non-polar solvent; and polishing particles modified with a silicon-containing compound, wherein the silicon-containing compound is represented by Formula 1,

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

Abstract: Methods for forming a semiconductor structure are provided. In one form, a method includes: providing a base; forming an initial pattern layer on the base; and performing atomic layer etching processing on a sidewall of the initial pattern layer one or more times to form a pattern layer, where the atomic layer etching processing includes: forming an organic layer on the sidewall of the initial pattern layer; and removing the organic layer. Generally, bond energy between an atom on an outermost surface of the sidewall of the initial pattern layer and an atom at an inner layer is less than bond energy between the atom at the inner layer. The organic layer usually includes an element that may react with the sidewall of the initial pattern layer, further reducing the bond energy between the atom on the outermost surface of the sidewall of the initial pattern layer and the atom at the inner layer.

Abstract: A patterning method of a film is disclosed. The method including: providing a film including a first surface; forming n etching barrier layers on the first surface of the film, and n is an integer larger than or equal to 2; and performing n etching processes on the film to form a recessed structure on the first surface using the n etching barrier layers as masks, the recessed structure includes n bottom surfaces respectively having different depths. Two adjacent etching processes of the n etching processes include a previous etching process and a subsequent etching process, and after the previous etching process is completed, a part of the n etching barrier layers is removed to form a mask for the subsequent etching process; a material of the part of the n etching barrier layers which is removed is different from a material of the mask of the subsequent etching process.

Abstract: A chemical mechanical polishing composition includes a liquid carrier and colloidal silica particles dispersed in the liquid carrier. The colloidal silica particles have a positive charge of at least 10 mV in the liquid carrier and may be characterized as having: (i) a number average aspect ratio of greater than about 1.25 and (ii) a normalized particle size span by weight of greater than about 0.42. The polishing composition may further optionally include an iron-containing accelerator and a tungsten etch inhibitor, for example, when the polishing composition is a tungsten CMP composition.

Abstract: A polishing composition according to the present invention contains silica, a nitrogen-containing alkaline compound, and hydrogen peroxide, in which a content of the hydrogen peroxide is more than 0% by mass and less than 0.03% by mass with respect to the total mass of the polishing composition, and a pH exceeds 9.

Abstract: An etching method includes: (a) providing a substrate including a silicon-containing film on a substrate support; (b) adjusting a temperature of the substrate support to ?20° C. or lower; (c) supplying a processing gas including a nitrogen-containing gas, into the chamber; (d) etching the silicon-containing film by using plasma generated from the processing gas. A recess is formed by etching the silicon-containing film, and a by-product containing silicon and nitrogen adheres to a side wall of the recess. The etching method further includes (e) setting at least one etching parameter of the temperature of the substrate support and the flow rate of the nitrogen-containing gas included in the processing gas, to adjust the width of the bottom of the recess according to an adhesion amount of the by-product, before (b).

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of forming fine patterns. The method for fabricating the semiconductor device according to the present invention may comprise forming an etch mask layer on an etch target layer; forming a spacer structure in which first spacers and second spacers are alternately disposed and spaced apart from each other on the etch mask layer; forming first spacer lines through selective etching of the first spacers; forming second spacer lines through selective etching of the second spacers; and etching the etch target layer to form a plurality of fine line patterns using the first and second spacer lines.

Abstract: A method includes etching a first region by plasma etching such that an upper surface of the first region is provided at a deeper position within a substrate than a second region; forming a deposit containing carbon on the substrate by forming plasma of a hydrocarbon gas inside a chamber of a plasma processing apparatus; and further etching the first region by plasma etching. In the forming of the plasma of the hydrocarbon gas, magnetic field distribution in which a horizontal component on an edge side of the substrate is larger than a horizontal component on a center of the substrate is formed by an electromagnet.

Abstract: A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Abstract: A disclosed etching method includes (a) generating plasma of a processing gas in a chamber of a plasma processing apparatus. The plasma is generated in a state where a substrate is placed on a substrate support having a lower electrode in the chamber. The substrate has a film and a mask. The mask is provided on the film. The etching method further includes (b) etching the film by supplying ions from the plasma to the substrate by periodically applying a pulse of a voltage to a lower electrode. In the operation (b), a level of a voltage of the pulse is changed at least once such that an absolute value of a negative potential of the substrate has a tendency to increase according to progress of etching of the film.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: Methods and systems for forming a structure including multiple carbon layers and structures formed using the method or system are disclosed. Exemplary methods include forming a first carbon layer and a second carbon layer, wherein a density and/or other property of the first carbon layer differs from the corresponding property of the second carbon layer.

Abstract: A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

Abstract: An object of the present invention is to provide a new polishing composition that contributes to improving the quality of a device. There is provided a polishing composition containing: an abrasive grain having an organic acid immobilized on a surface thereof; a first water-soluble polymer having a sulfonic acid group or a group having a salt thereof, or a carboxyl group or a group having a salt thereof; a second water-soluble polymer different from the first water-soluble polymer; a nonionic surfactant; and an aqueous carrier, wherein the polishing composition is used for polishing an object to be polished.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: In an embodiment, a method includes: receiving, within a processing chamber, a wafer with a photoresist mask above a metal layer, wherein the processing chamber is connected to a gas source; applying an etchant configured to etch the metal layer in accordance with the photoresist mask within the processing chamber; and applying gas from the gas source to perform plasma ashing in the processing chamber.

Abstract: Chemical mechanical planarization (CMP) polishing compositions, methods and systems are provided to reduce oxide trench dishing and improve over-polishing window stability. High and tunable silicon oxide removal rates, low silicon nitride removal rates, and tunable SiO2:SiN selectivity are also provided. The compositions use a unique combination of abrasives such as ceria coated silica particles and chemical additives such as maltitol, lactitol, maltotritol or combinations as oxide trench dishing reducing additives.

Abstract: Aspects generally relate to methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers. In one aspect, film stress is altered while facilitating enhanced etch selectivity. In one implementation, a method of processing a substrate includes depositing one or more amorphous carbon hardmask layers onto the substrate, and conducting a rapid thermal anneal operation on the substrate after depositing the one or more amorphous carbon hardmask layers. The rapid thermal anneal operation lasts for an anneal time that is 60 seconds or less. The rapid thermal anneal operation includes heating the substrate to an anneal temperature that is within a range of 600 degrees Celsius to 1,000 degrees Celsius. The method includes etching the substrate after conducting the rapid thermal anneal operation.