Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract: A method for shielding a compartment in a module of an electronic device includes molding the module using a mold material that activates when a laser is applied. The method also includes cutting a trench on the mold of the module around a certain portion of the module using the laser. The method further includes plating the trench using a certain metal. The method also includes filling the trench with a filler material. The method further includes encapsulating the module, the mold, the trench, and the filler material.

Abstract: The application describes improvements to (MEMS) transducers (100) having a flexible membrane (301) with a membrane electrode (302), especially where the membrane is crystalline or polycrystalline and the membrane electrode is metal or a metal alloy. Such transducers may typically include a back-plate having at least one back-plate layer (304) coupled to a back-plate electrode (303), with a plurality of holes (314) in the back-plate electrode corresponding to a plurality back-plate holes (312) through the back-plate. In embodiments of the invention the membrane electrode has at least one opening (313) in the membrane electrode wherein, at least part of the area of the opening corresponds to the area of at least one back-plate hole, in a direction normal to the membrane, and there is no hole in the flexible membrane at said opening in the membrane electrode. There may be a plurality of such openings. The openings effectively allow a reduction in the amount of membrane electrode material, e.g.

Abstract: This adhesive contains an epoxy compound, a cationic catalyst, and an acrylic resin that includes acrylic acid and an acrylic acid ester having a hydroxyl group. The acrylic acid in the acrylic resin reacts with the epoxy compound, creating a link between the acrylic resin island part and the epoxy compound sea part, and strengthening the anchoring effect with respect to the epoxy compound sea part by roughening the surface of an oxide film. Furthermore, the hydroxyl-group-containing acrylic acid ester in the acrylic resin becomes electrostatically adhesive to wiring due to the polarity of the hydroxyl group. Excellent adhesive strength can be obtained by adhering, in this way, the entire cured product composed of the acrylic resin island part and the epoxy compound sea part to the oxide film.

Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.

Abstract: A light emitting device includes a light emitting layer, a substrate that is transparent to an emission wavelength of the light emitting layer and positioned to receive an emission wavelength from the light emitting layer, a convex pattern including a collection of a plurality of convex portions discretely arranged on a front surface of the substrate with a first pitch, an n type nitride semiconductor layer located on the front surface of the substrate to cover the convex pattern and a p type nitride semiconductor layer located on the light emitting layer. The light emitting layer is located on the n type semiconductor layer. Each of the convex portions includes a sub convex pattern comprising a plurality of fine convex portions discretely formed at the top of the convex portion with a second pitch smaller than the first pitch, and a base supporting the sub convex pattern.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.

Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.

Abstract: According to one embodiment, a semiconductor device includes a substrate; a first structure; a second structure; a step; an insulating layer; a first pillar; a second pillar; a first contact portion; and a second contact. The first structure includes a first electrode layer and a first insulator. The first structure has a first terrace on a surface of the first insulator. The second structure includes a second electrode layer and a second insulator. The second structure has a second terrace on a surface of the second insulator. The second contact portion is electrically connected to the second electrode layer via the second terrace. The first contact portion is located between the step and the first pillar. The step is located between the first contact portion and the second pillar.

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

Abstract: A manufacturing method of a mother substrate assembly includes forming a metal layer on substantially an entire surface of a transparent substrate including a cell area including a non-display area and a display area, an align key area, and a substrate area surrounding the cell area and the align key area, etching the metal layer to form an align key in the align key area, etching the metal layer to form a reflection part in the non-display area, and etching the metal layer in the display area to form a metal nanowire in the display area.

Abstract: After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.

Abstract: Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a conductive layer, which is disposed between a first node and a second node in a semiconductor chip, and which has a width that is at least a first threshold value but not more than a second threshold value, the first threshold value and the second threshold value being less than the minimum width according to the design rules that can ensure that the conductive layer is patterned such that the first node and the second node are electrically short-circuited, and a reader which provides an identification key by identifying if there is a short circuit between the first node and the second node.

Abstract: A method of forming a semiconductor device and resulting structures having stacked nanosheets with a wrap-around inner spacer by forming a nanosheet stack disposed above a substrate; forming a top sacrificial layer on a top surface of the nanosheet stack; forming a sidewall sacrificial layer on two opposite sidewalls of the nanosheet stack, such that a first and a second end of a first vertically-stacked nanosheet are exposed; removing the sidewall sacrificial layer, a portion of a first and a second end of a first sacrificial layer, and a portion of a first and a second end of a top sacrificial layer to expose portions of the first vertically-stacked nanosheet; and forming an inner spacer region on the first vertically-stacked nanosheet to replace the removed sidewall sacrificial layer, the removed portions of the first sacrificial layer, and the removed portions of the top sacrificial layer.

Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads are also embedded in the mold compound and electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Abstract: According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.