Patents Examined by Rodolfo D Fortich
-
Patent number: 9685506Abstract: There are disclosed herein implementations of an insulated-gate bipolar transistor (IGBT) having an inter-trench superjunction structure. Such an IGBT includes a drift region having a first conductivity type situated over a collector having a second conductivity type. The IGBT also includes first and second gate trenches extending through a base having the second conductivity type into the drift region, the first and second gate trenches each being bordered by an emitter diffusion having the first conductivity type. In addition, the IGBT includes an inter-trench superjunction structure situated in the drift region between the first and second gate trenches.Type: GrantFiled: December 31, 2015Date of Patent: June 20, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
-
Patent number: 9679949Abstract: An organic light emitting display device is disclosed. The organic light emitting display device includes a first sub-pixel that includes a first emission region which makes a first color, a second sub-pixel that is disposed adjacent to the first sub-pixel, and includes a second emission region which makes a second color, a third sub-pixel that is disposed adjacent to the first sub-pixel, and includes a third emission region which makes a third color, and a fourth sub-pixel that is disposed adjacent to the second sub-pixel and the third sub-pixel, and includes a fourth emission region which makes a fourth color. At least one of the first to fourth sub-pixels includes a transmission region which cannot emit light and through which external light is transmitted. The transmission region is surrounded by at least one of the first to fourth emission regions.Type: GrantFiled: October 17, 2014Date of Patent: June 13, 2017Assignee: Samsung Display Co., Ltd.Inventor: Jun-Heyung Jung
-
Patent number: 9673292Abstract: A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.Type: GrantFiled: November 25, 2015Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
-
Patent number: 9673414Abstract: An organic light-emitting diode and a method for preparing the same are disclosed. The organic light-emitting diode at least comprises a luminescent layer between an anode and a cathode, and the organic light-emitting diode further comprises at least two electron transport layers set between the luminescent layer and the cathode and an N-type doped layer set between every two adjacent electron transport layers. For the organic light-emitting diode of the invention, an electron transport material and an N-type dopant are sequentially evaporated in turn, and the electron injection and transportation capacity is improved by forming an N-type doping-like effect from interface dope effect and the diffusion of an N-type dopant, so that carrier concentration can be balanced, exciton utilization can be improved, and the photoelectric properties of the OLED device can be improved.Type: GrantFiled: October 31, 2014Date of Patent: June 6, 2017Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Juanjuan Bai, Taegyu Kim, Haidong Wu
-
Patent number: 9673205Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.Type: GrantFiled: August 24, 2015Date of Patent: June 6, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Ming Wu, Wei-Cheng Wu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai, Ru-Liang Lee, Harry Hak-Lay Chuang
-
Patent number: 9666574Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.Type: GrantFiled: November 30, 2015Date of Patent: May 30, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Yi Lee, Shih-Fen Huang, Pei-Lun Wang, Dah-Chuen Ho, Yu-Chang Jong, Mohammad Al-Shyoukh, Alexander Kalnitsky
-
CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
Patent number: 9666492Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.Type: GrantFiled: July 13, 2015Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau -
Patent number: 9659885Abstract: This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.Type: GrantFiled: September 23, 2014Date of Patent: May 23, 2017Assignee: Intel CorporationInventor: Chuan Hu
-
Patent number: 9659889Abstract: This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal.Type: GrantFiled: December 20, 2013Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Mihir Oka, Xavier Brun, Dingying David Xu, Edward Prack, Kabirkumar Mirpuri, Saikumar Jayaraman
-
Patent number: 9660090Abstract: An array substrate having a thin film transistor with an oxide semiconductor layer, wherein the thin film transistor is in a device area of a pixel region; the substrate comprising a light-shielding pattern on the array substrate in the device area; an auxiliary line connected to a light-shielding pattern and supplying a constant voltage to the light-shielding pattern, wherein the auxiliary line is parallel to and spaced apart from one of the gate and data lines; a buffer layer on the light-shielding pattern and a surface of the array substrate, wherein the oxide semiconductor layer is on the buffer layer and the light-shielding pattern; an inter-insulating layer on the buffer layer, wherein the oxide semiconductor layer includes an active portion located entirely on the light-shielding pattern and having a channel formed thereon, and conductive portions located on sides of the active portion.Type: GrantFiled: October 20, 2014Date of Patent: May 23, 2017Assignee: LG DISPLAY CO., LTD.Inventor: Joong-Sun Yoon
-
Patent number: 9659955Abstract: A method of forming a device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, and forming an aluminum oxide layer on sidewall surfaces of the sacrificial material layers and on sidewall surfaces of the insulating layers around the memory opening. First aluminum oxide portions of the aluminum oxide layer are located on sidewall surfaces of the sacrificial material layers, and second aluminum oxide portions of the aluminum oxide layer are located on sidewalls of the insulating layers. The method also includes removing the second aluminum oxide portions at a greater etch rate than the first aluminum oxide portions employing a selective etch process, such that all or a predominant portion of each first aluminum oxide portion remains after removal of the second aluminum oxide portions.Type: GrantFiled: October 28, 2015Date of Patent: May 23, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Rahul Sharangpani, Sateesh Koka, Raghuveer S. Makala, Somesh Peri, Senaka Kanakamedala
-
Patent number: 9656854Abstract: Disclosed herein are a microelectromechanical systems (MEMS) microphone with a dual-back plate, and a method of manufacturing the same. The MEMS microphone according to an exemplary embodiment of the present invention includes: a substrate having a first back plate formed at a central portion thereof; a membrane plate disposed on first support parts formed at both sides on the substrate and vibrated depending on external sound pressure; and a second back plate disposed on second support parts formed at both sides of the membrane plate.Type: GrantFiled: November 29, 2012Date of Patent: May 23, 2017Assignee: KOREA INSTITUTE OF MACHINERY & MATERIALSInventors: Shin Hur, Young Do Jung, Young Hwa Lee, Jun Hyuk Kwak, Chang-Hyeon Ji
-
Patent number: 9653414Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.Type: GrantFiled: July 22, 2015Date of Patent: May 16, 2017Assignee: NXP B. V.Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
-
Patent number: 9653371Abstract: An underfill material enabling voidless packaging and excellent solder bonding properties, and a method for manufacturing a semiconductor device using the same are provided. An underfill material is used which contains an epoxy resin and a curing agent, and a time for a reaction rate to reach 20% at 240° C. calculated by Ozawa method using a differential scanning calorimeter is 2.0 sec or less and a time for the reaction rate to reach 60% is 3.0 sec or more. This enables voidless packaging and excellent solder connection properties.Type: GrantFiled: September 10, 2014Date of Patent: May 16, 2017Assignee: DEXERIALS CORPORATIONInventor: Hironobu Moriyama
-
Patent number: 9627377Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.Type: GrantFiled: November 11, 2014Date of Patent: April 18, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Marc Adam Bergendahl, Kangguo Cheng, David Vaclav Horak, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Chih-Chao Yang, Charles William Koburger, III, Xiuyu Cai, Ruilong Xie
-
Patent number: 9627321Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.Type: GrantFiled: March 31, 2015Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Boyan Boyanov, Kanwal Jit Singh
-
Patent number: 9627571Abstract: An optical fiber is provided between a photodiode and a semiconductor active portion of a wide gap semiconductor element forming portion such that emitted light at the time of light emission of the semiconductor active portion of the wide gap semiconductor element forming portion is incident from an incident surface of the optical fiber, and is received from an emitting surface to the photodiode through the optical fiber. Specifically, the incident surface of the optical fiber is arranged so as to be opposed to a side surface portion of the wide gap semiconductor element forming portion, so that the emitted light at the time of light emission of the wide gap semiconductor element is incident on the incident surface.Type: GrantFiled: March 24, 2014Date of Patent: April 18, 2017Assignee: Mitsubishi Electric CorporationInventors: Naoto Kaguchi, Yoichiro Tarui
-
Patent number: 9627432Abstract: A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.Type: GrantFiled: March 30, 2016Date of Patent: April 18, 2017Assignee: Sony CorporationInventor: Yoshiharu Kudoh
-
Patent number: 9620623Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.Type: GrantFiled: July 29, 2014Date of Patent: April 11, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Tatsuya Honda
-
Patent number: 9620512Abstract: A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.Type: GrantFiled: October 28, 2015Date of Patent: April 11, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Hiroaki Koketsu, Fumiaki Toyama, Junji Oh