Patents Examined by Roshn Varghese
  • Patent number: 10015884
    Abstract: Disclosed herein is a printed circuit board (PCB) including an embedded electronic component, including: a core having a cavity; an electronic component inserted into the cavity having a rough surface formed on surfaces of external electrodes provided on both lateral portions thereof, a low rough surface being formed in a portion of the rough surfaces; insulating layers laminated on upper and lower portions of the core and bonded to an outer circumferential surface of the electronic component insertedly positioned in the cavity; and an external circuit pattern provided on the insulating layers.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: July 3, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Eun Lee, Yee Na Shin, Yul Kyo Chung, Doo Hwan Lee
  • Patent number: 9996653
    Abstract: The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace segments that deviate the signal trace away from the source of the routing restriction.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: June 12, 2018
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Lin Shen, Yongming Xiong, Shahbaz Mahmood, Maurilio De Nicolo
  • Patent number: 9992858
    Abstract: A printed circuit board includes a first printed circuit substrate and a second printed circuit substrate. The first printed circuit substrate includes a substrate layer and a first conductive circuit layer. The first conductive circuit layer is formed on the substrate layer. The substrate layer includes at least two first grooves. The first conductive circuit layer includes at least one signal wire. The first grooves are defined in both sides of the signal wire. The second printed circuit substrate is formed on the first printed circuit substrate. The second circuit substrate includes a third copper layer. A second groove is defined in the third copper layer. The first grooves are opposite to the second groove. The first grooves and the second groove form a space.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: June 5, 2018
    Assignees: Avary Holding (Shenzhen) Co., Limited, HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD
    Inventors: Ming-Jaan Ho, Xian-Qin Hu, Yi-Qiang Zhuang, Fu-Wei Zhong
  • Patent number: 9981421
    Abstract: Systems and processes that integrate thermoplastic and shape memory alloy materials to form an adaptive composite structure capable of changing its shape. For example, the adaptive composite structure may be designed to serve as a multifunctional adaptive wing flight control surface. Other applications for such adaptive composite structures include in variable area fan nozzles, winglets, fairings, elevators, rudders, or other aircraft components having an aerodynamic surface whose shape is preferably controllable. The material systems can be integrated by means of overbraiding (interwoven) with tows of both thermoplastic and shape memory alloy materials or separate layers of each material can be consolidated (e.g., using induction heating) to make a flight control surface that does not require separate actuation.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: May 29, 2018
    Assignee: The Boeing Company
    Inventors: Jeffery L. Marcoe, Sahrudine Apdalhaliem, Moushumi Shome
  • Patent number: 9980371
    Abstract: A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: May 22, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Takayuki Katsuno, Yuki Ito, Takeshi Furusawa, Takema Adachi
  • Patent number: 9978486
    Abstract: A resistor support assembly includes first, second, third, and fourth support members. Each of the first and second support members includes one or more resistor contact regions and apertures extending therethrough. Each third support member is at least partially disposed within one of the apertures of one of the first support members and one of the apertures of one of the second support members. Recesses may be formed in the resistor contact regions of the first and the second support members, and one or more load resistors may be at least partially disposed within the recesses. The resistor support assembly may be used to mount one or more load resistors to a printed circuit board, without obstructing airflow through hollow portions of the load resistors. To reduce parasitic capacitance and inductance, the first support members and the second support members are formed from non-conductive materials.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: May 22, 2018
    Assignee: Fluke Corporation
    Inventors: Mark Steven Buckner, Steven Wayne Higgins, Donald A. Gessling, Bryan Charles Hoog, Michael A. Schoch
  • Patent number: 9978515
    Abstract: An electronic component unit includes a substrate including principal surfaces opposing each other and side surfaces between the principal surfaces, and components mounted on the principal surface of the substrate. The side surfaces include first side surfaces formed before the components are mounted and second side surfaces formed after the components are mounted. As viewed from a line normal to the principal surface of the substrate, distances between the first side surfaces and the components are different from distances between the second side surfaces and the components.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 22, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuto Ogawa, Isao Kato
  • Patent number: 9949388
    Abstract: A waterproof ventilator includes: an outer hollow body including: an internal space; a side with an outer opening adopted not to be covered with a water film at a lower portion thereof; and a bottom; and an inner hollow body including an internal space, at least a part of which is housed in the outer hollow body, and including: an outer surface disposed so as not to cause a water film to stay in a gap with an inner surface of the outer hollow body; an inner opening provided at a position not to be hit directly with water entering into the internal space of the outer hollow body through the outer opening and adopted not to be covered with a water film; an upper opening provided at an upper side than the inner opening and communicating with an exterior of the outer hollow body; and a bottom.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: April 17, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuki Maeda, Taro Ueda, Hidetaka Yamauchi
  • Patent number: 9942984
    Abstract: A signal attenuation reduction structure for a flexible circuit board includes a conductive paste coating zones formed on surfaces of high-frequency signal lines and an insulation layer formed on a dielectric layer of the flexible circuit board such that the conductive paste coating zone corresponds to a pair of high-frequency signal lines or covers a plurality of pairs of the high-frequency signal lines. An anisotropic conductive film is formed on surfaces of the insulation layer and the conductive paste coating zone of the flexible circuit board. The anisotropic conductive film is pressed to bond between the conductive paste coating zone and a shielding layer such that the conductive paste coating zone and the shielding layer achieve electrical connection therebetween in a vertical direction through the anisotropic conductive film.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 10, 2018
    Assignee: Advanced Flexible Circuits Co., Ltd.
    Inventors: Kuo-Fu Su, Chih-Heng Chuo, Gwun-Jin Lin
  • Patent number: 9912132
    Abstract: A shielded conduction path that makes it possible to reduce the diameter of a portion where a braided wire is fixed to a pipe. The shielded conduction path includes a pipe that has a shielding function, reduced diameter portions that are formed in the outer circumference of the pipe, braided wires that have a shielding function and are arranged such that the base end portions thereof envelop the outer circumference of the reduced diameter portions, crimp rings that are arranged so as to envelop the outer circumference of the base end portions of the braided wires and fix the braided wires to the reduced diameter portions, and a conduction path main body that is inserted into the pipe and into the braided wires.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: March 6, 2018
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Ryo Kuroishi, Hirokazu Nakai
  • Patent number: 9907192
    Abstract: An electronic apparatus includes a housing that houses an electronic component, and a first cover and a second cover that cover the housing, wherein the electronic component is oriented along and on an inner side of a first sidewall of the first cover, wherein a side surface of the electronic component that faces the first sidewall has a cut, wherein the first cover has a recess that is depressed from the first sidewall toward the inner side in such a manner as to conform to the cut, and wherein the first cover is fastened at the recess to the second cover with a fastening member.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: February 27, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hiromu Shoji, Tsubasa Hashimoto, Hiroshi Nakamura
  • Patent number: 9903024
    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Yi Wu, Chun-Hung Lu
  • Patent number: 9893482
    Abstract: A branched electrical system is adapted for providing multiple users with access to high and/or low voltage electrical power in work areas or high density seating areas, such as stadium or theater seating, work rooms, lecture halls, and public transportation vehicles. The system includes a main line and a plurality of branch lines, each branch line having at least one high voltage or low voltage electrical receptacle that is accessible to a user located at the seating, such as for powering a portable electronic device. The branch lines may be coupled to the main line via a splice or other electrical-mechanical connection.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: February 13, 2018
    Inventors: Norman R. Byrne, Daniel P. Byrne, Timothy J. Warwick, Thomas A. Petersen, Randell E. Pate
  • Patent number: 9887529
    Abstract: A wire harness having at least wire harness assembly having a splice of at least three shielded wire cables is presented. The assembly includes a flexible insulation layer wrapped about the joined core conductors of the three cables, a flexible conductive layer wrapped about the shield conductors of the cables, and a section of dual wall heat shrink tubing enclosing the flexible conductive layer and portions of the insulative jackets of the cables. The flexible conductive layer does not include any solder.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: February 6, 2018
    Assignee: Delphi Technologies, Inc.
    Inventors: Brian K. Dew, Bruce D. Taylor
  • Patent number: 9888618
    Abstract: Disclosed is a shielded harness (100) which includes a low-voltage cable (101) and a high-voltage cable (102) to which a voltage higher than that of the low-voltage cable (101) is applied, and into which the low-voltage and the high-voltage cables (101 and 102) are bundled, the shielded harness (100) including: a cylindrical shield member (103) that covers the circumference of the high-voltage cable (102) to form an gap so as to electromagnetically shield; and a cylindrical protective member (104) that covers the circumference of the shield member (103) and the low-voltage cable (101). The shield member (103) and the protective member (104) are partially bonded or welded together.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: February 6, 2018
    Assignee: Yazaki Corporation
    Inventor: Maki Yamada
  • Patent number: 9872401
    Abstract: A circuit substrate includes a core substrate having cavity penetrating through the core substrate, a metal block accommodated in the cavity of the core substrate, a first build-up layer including an insulating layer and laminated on first side of the core substrate such that the first build-up layer is covering the cavity on the first side of the core substrate, and a second build-up layer including an insulating layer and laminated on second side of the core substrate such that the second build-up layer is covering the cavity on the second side of the core substrate, and a filling resin filling gap formed between the cavity and block positioned in the cavity of the core substrate. The block has roughened surfaces such that the roughened surfaces are in contact with the insulating layers in the first and second build-up layers on the first and second sides of the core substrate.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: January 16, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Mitsuhiro Tomikawa, Koji Asano
  • Patent number: 9865377
    Abstract: A wire bundle includes insulated wires. The insulated wires each includes a conductor core covered with an insulator and is quad-twisted to form the wire bundle. The wire bundle has an annular shape including an inner perimeter and an outer perimeter in a cross section perpendicular to an axis line of the wire bundle. A shape of the outer perimeter is a square or a quasi-square. The quasi-square is a shape formed by curving at least one side of a square to a radial inside direction of the annular shape in the cross section. The insulated wires each has, in the cross section, a shape connecting a plurality of vertexes including two adjacent vertexes of the square or the quasi-square and two vertexes present on the inner perimeter.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: January 9, 2018
    Assignee: YAZAKI ENERGY SYSTEM CORPORATION
    Inventors: Kouji Nakamura, Takahiro Suzuki
  • Patent number: 9867277
    Abstract: Representative implementations of devices and techniques provide improved electrical performance of components, such as chip dice, for example, disposed on different layers of a multi-layer printed circuit board (PCB). In an example, the components may be embedded within layers of the PCB. An insulating layer located between two component layers or sets of layers includes a conductive portion that may be strategically located to provide electrical connectivity between the components. The conductive portion may also be arranged to improve thermal conductivity between points of the PCB.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: January 9, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Andrew Roberts
  • Patent number: 9854720
    Abstract: Disclosed herein is an electromagnetic wave shielding dielectric film. The electromagnetic wave shielding dielectric film includes a lower layer and an upper layer. The lower layer is formed of a dielectric in a plate shape. The upper layer is formed of a dielectric stacked on the lower layer, and is configured to form a periodic pattern of protrusion and depression structures.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: December 26, 2017
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Jeonghoon Yoo, Hyundo Shin, Kyoungsik Kim
  • Patent number: 9843233
    Abstract: An insulated electric wire includes a rectangular conductor and an insulation film disposed on the periphery of the rectangular conductor. The insulation film is characterized by: the provision of a resin containing an imide structure within a molecule; and a peak value of less than 1.0 for the loss tangent tan ?, which is represented by the ratio between the loss elastic modulus and the storage elastic modulus, as measured in the 50 DEG C. to 400 DEG C. range.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 12, 2017
    Assignee: HITACHI METALS, LTD.
    Inventors: Shuta Nabeshima, Yuki Honda, Hideyuki Kikuchi