Patents Examined by S. Rosasco
  • Patent number: 7316870
    Abstract: Isolated dark features, e.g. contact holes or lines, are exposed in a double exposure, using different illumination settings in the two exposures.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: January 8, 2008
    Assignee: ASML Netherlands B.V.
    Inventors: Markus Franciscus Antonius Eurlings, Jozef Maria Finders
  • Patent number: 7314689
    Abstract: A method and system is disclosed for processing one or more oblique features on a mask or reticle substrate. After aligning the mask or reticle substrate with a predetermined reference system, an offset angle of a feature to be processed on the mask or reticle substrate with regard to either the horizontal or vertical reference direction of the predetermined reference system is determined. The mask or reticle substrate is rotated in a predetermined direction by the offset angle; and the feature on the mask or reticle substrate is processed using the predetermined reference system wherein the feature is processed in either the horizontal or vertical reference direction thereof.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: January 1, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Burn Jeng Lin, Ping Yang, Hong Chang Hsieh, Yao Ching Ku, Chin Hsian Lin, Chiu Shan Yoo
  • Patent number: 7314690
    Abstract: In a method of producing a photomask (10) in which a light-transmissive substrate (1) is formed thereon with a chromium pattern (21) having a global opening ratio difference in its plane on the light-transmissive substrate (1), use is made, as an etching mask for a chromium film (2), of an etching mask pattern (31) made of an inorganic-based material having a resistance against etching of the chromium film (2). Dry etching of the chromium film (2) is carried out under a condition selected from conditions that cause damage to a resist pattern (41) to a degree which is unallowable when etching the chromium film (2) using the resist pattern (41) as a mask.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: January 1, 2008
    Assignee: Hoya Corporation
    Inventors: Yasushi Okubo, Mutsumi Hara
  • Patent number: 7312004
    Abstract: The attenuation and phase shift properties of an embedded attenuated phase shift mask (EAPSM) may be independently selected. After or during plowing of regions of an embedded phase shift layer, exposed regions of a substrate are etched to a predetermined depth. Additional regions of the embedded phase sift layer are then exposed and trimmed to a predetermined thickness for providing the desired amount of attenuation, with the final etched depth of the substrate compensating for the change of relative phase shift caused by trimming of the phase shift layer. A matrix test device having a plurality of cells with different levels of attenuation and/or phase shift may then be fabricated on a single EAPSM blank.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: December 25, 2007
    Assignee: Photronics, Inc.
    Inventor: Guangming Xiao
  • Patent number: 7312003
    Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: December 25, 2007
    Assignee: Synopsys, Inc.
    Inventors: Michel L. Cote, Christophe Pierrat
  • Patent number: 7312021
    Abstract: A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: December 25, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Chung-Hsing Chang, Chih-Cheng Chin, Wen-Chuan Wang, Chi-Lun Lu, Sheng-Chi Chin, Chin-Hsiang Lin
  • Patent number: 7309549
    Abstract: A method for minimizing damage to a substrate while repairing a defect in a phase shifting mask for an integrated circuit comprising locating a bump defect in a phase shifting mask, depositing a first layer of protective coating to an upper surface of the bump defect, depositing a second layer of protective coating to areas of the phase shifting mask adjacent the bump defect, etching the first layer of protective coating and removing the bump defect.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: December 18, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Baorui Yang, Matthew Lamantia
  • Patent number: 7306882
    Abstract: A phase shift mask includes a quartz substrate having a main surface partially dug, and a Cr film deposited on the main surface. The dug portion includes an undercut provided such that the Cr film partially serves as an eaves, and the Cr film has a ? opening exposing a portion of the dug portion, and a first subopening exposing an end of the dug portion.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: December 11, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Satoshi Aoyama
  • Patent number: 7306881
    Abstract: A method forms patterns on a substrate by exposing the substrate a first time and exposing the substrate a second time using a mask containing gray-tone features. The gray-tone features locally adjust an exposure dose in regions corresponding to features defined in the primary exposure. Moreover, the gray-tone features enable the forming of features having different critical dimensions on a substrate. The gray-tone features may be sub-resolution features and formed by pixellation. The trim mask containing gray-tone features may have regions with different transmissivities.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: December 11, 2007
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael Fritze, Brian Tyrrell
  • Patent number: 7303844
    Abstract: Marking system for a semiconductor wafer to identify problems in mask layers. A method for forming a mask which includes the step of first creating at least one drawing layer that defines changes to the structures to be formed on the surface of a semiconductor substrate at one step in the processing thereof, which step involves the use of a mask. The at least one drawing layer will define a pattern region that will either result in removal of the material from the semiconductor substrate in the defined pattern region, or removal of matter from the semiconductor substrate around the defined pattern region. An indicator area is created in the at least one drawing layer, the indicator area having an indicator region disposed therein that will result in removal of material from around the indicator region regardless of whether the mask is a dark tone mask or a clear tone mask, the indicator region appearing in the negative if the mask is a dark tone mask.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: December 4, 2007
    Assignee: Silicon Labs CP, Inc.
    Inventor: John Ellis
  • Patent number: 7300724
    Abstract: An extreme ultraviolet lithography (EUVL) mask blank may include a multilayer (ML) capping structure on the ML reflective coatings on the substrate. The ML capping structure may include alternating layers of a capping material, e.g., ruthenium, and a material with a lower EUV absorption coefficient, e.g., silicon. The top layer of the ML structure may be a layer of the capping material. Capping interfaces between the layers may provide constructive interference of reflected light.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: November 27, 2007
    Assignee: Intel Corporation
    Inventor: Pei-Yang Yan
  • Patent number: 7294438
    Abstract: This invention is a method of producing a reflective mask comprising a substrate, a reflective multilayer film formed on the substrate to reflect exposure light, and at least one layer formed on the reflective multilayer film to define a nonreflecting region for the exposure light. The method comprises the steps of: (a) patterning a layer formed on and adjacent to a topmost layer of the reflective multilayer film; and (b) removing a reaction product produced following patterning in the step (a) and deposited on an exposed surface of the reflective multilayer film which is exposed as a result of patterning in the step (a). The step (a) may be performed by the use of an oxygen-containing plasma process.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: November 13, 2007
    Assignee: Hoya Corporation
    Inventor: Tsutomu Shoki
  • Patent number: 7294437
    Abstract: Systems and techniques to quickly and accurately model a transmitted electromagnetic field through a mask, to design a mask, and to create a library of corrections including edge corrections, edge-to-edge corrections, and corner corrections.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: November 13, 2007
    Assignee: Intel Corporation
    Inventors: Peng Liu, Vivek Singh
  • Patent number: 7291425
    Abstract: The invention includes, for example, a radiation patterning tool which can be utilized to form relatively circular contacts in situations in which an array of contacts has a different pitch along a row of the array than along a column of the array. An alternating phase shift can give a well-defined contact in the small pitch (dense) direction. Rim shifters are added in the larger pitch direction to force the circular form of the contact openings. In further aspects of the invention, side-lobe-suppressing patterns can be added between adjacent rims. The invention also includes methods of forming radiation patterning tools.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: November 6, 2007
    Assignee: Micron Technology, Inc.
    Inventor: H. Daniel Dulman
  • Patent number: 7288344
    Abstract: Systems and techniques for accommodating diffraction in the printing of features on a substrate. In one implementation, a method includes identifying a pair of features to be printed using a corresponding pair of patterning elements and increasing a separation distance between the pair of patterning elements while maintaining the sufficiently small pitch between the corresponding imaged features. The pitch of the pair of features can be sufficiently small that, upon printing, diffraction will make a separation between the features smaller than a separation between the corresponding pair of patterning elements.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: October 30, 2007
    Assignee: Intel Corporation
    Inventors: Rex K. Frost, Swaminathan (Sam) Sivakumar
  • Patent number: 7282308
    Abstract: In the formation of a halftone type phase shift mask, a reactive gas introduction inlet and an inert gas introduction inlet are provided so as to introduce the respective gases separately and by using a reactive low throw sputtering method a molybdenum silicide based phase shifter film is formed. Thereby, it becomes possible to provide a halftone type phase shift mask, which is applicable to an ArF laser or to a KrF laser, by using molybdenum silicide based materials.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 16, 2007
    Assignees: Ulvac Coating Corporation, Renesas Technology Corp.
    Inventors: Susumu Kawada, Akihiko Isao, Nobuyuki Yoshioka, Kazuyuki Maetoko
  • Patent number: 7282307
    Abstract: An EUV mask (10, 309) includes an opening (26) that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. A first embedded layer (20) and a second embedded layer (21) may be provided between a lower multilayer reflective stack (14) and an upper multilayer reflective stack (22) to ensure an appropriate and accurate depth of the opening (26), while allowing for defect inspection of the EUV mask (10, 309) and optional defect repair. An optional ARC layer (400) may be deposited in region (28) to reduce the amount of reflection within dark region (28). Alternately, a single embedded layer of hafnium oxide, zirconium oxide, tantalum silicon oxide, tantalum oxide, or the like, may be used in place of embedded layers (20, 21). Optimal thicknesses and locations of the various layers are described.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: October 16, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Scott D. Hector, Sang-In Han
  • Patent number: 7282306
    Abstract: A phase shift mask may include boundaries between phase shift regions with continuous sloped phase edges. The continuous sloped phase edges may be produced by introducing a predetermined degree of defocus into a beam used during production of the mask to image the pattern on the mask. Such a phase shift mask may be “trimless”, i.e., not require a corresponding binary “trim” mask for a second exposure to remove phase conflicts after exposure with the phase shift mask.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: October 16, 2007
    Assignee: Intel Corporation
    Inventors: Matt F. Vernon, Wen-Hao Cheng
  • Patent number: 7282305
    Abstract: A reflective mask blank has a substrate (1) and a reflective multilayer film (3) formed on the substrate to reflect exposure light. The substrate has a base pattern (2) formed by a predetermined irregularity. On a surface of the reflective multilayer film formed on the base pattern, a step portion corresponding to the base pattern is formed as a programmed defect.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: October 16, 2007
    Assignee: Hoya Corporation
    Inventors: Tsutomo Shoki, Ryo Ohkubo, Takeru Kinoshita
  • Patent number: 7279252
    Abstract: The invention relates to the manufacture of a substrate which is particularly suitable for EUV micro-lithography and comprises a base layer of low coefficient of thermal expansion (CTE) onto which at least one cover layer made of a semiconductor material is applied. Preferably, the cover layer is a silicon layer, preferably applied by ion beam sputtering. By an additional ion beam figuring treatment substrates of extremely accurate shape and extremely low roughness can be prepared.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: October 9, 2007
    Assignee: Schott AG
    Inventors: Lutz Aschke, Markus Schweizer, Jochen Alkemper, Axel Schindler, Frank Frost, Thomas Haensel, Renate Fechner