Abstract: A method, non-transitory computer readable medium, and storage management computing device that obtains an information lifecycle management (ILM) policy. A data protection scheme to be applied at a storage node computing device level is determined and a plurality of storage node computing devices are identified based on an application of the ILM policy to metadata received from one of the storage node computing devices and associated with an object ingested by the one of the storage node computing devices. The one of the storage node computing devices is instructed to generate one or more copies of the object or fragments of the object according to the data protection scheme and to distribute the object copies or one of the object fragments to one or more other of the storage node computing devices to be stored by at least the one or more other storage node computing devices on one or more disk storage devices.

Abstract: In group-wise interleaving, interleaving of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15 is performed in a unit of a bit group of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code that has undergone group-wise interleaving is returned to an original arrangement. The technology can be applied to a case of transmitting data using the LDPC code. The data processing device and data processing method can ensure excellent communication quality in data transmission using an LDPC code.

Abstract: A data storage device including a flash memory and a controller. The controller performs a first read operation on the pages of a first block of a first block group, and performs a maintenance process to determine whether the first group read count of the first block group is greater than a read threshold when the first read operation is finished. The controller scans the blocks of the first block group to obtain a plurality of first error bit numbers when the first group read count is greater than the read threshold, and updates the block corresponding to the first error bit number that is greater than an error-bit threshold.

Abstract: A method for transmitting a plurality of uplink messages may include transmitting a first uplink message to a sink device and monitoring a feedback channel for feedback information from the sink device during one or more default feedback reception periods associated with the first uplink message. The method may further include skipping monitoring of the feedback channel during the remaining default feedback reception periods associated with the first uplink message if a number of consecutive default feedback reception periods containing positive feedback information exceeds a threshold, updating the threshold based on a channel quality measure, transmitting a second uplink message, and monitoring or skipping monitoring of the feedback channel during default feedback reception periods associated with a second uplink message based on the updated threshold.

Abstract: The present invention is applicable to the field of error correction coding, and provides a circuit, an encoder and a method for parallel BCH coding. The method comprises: performing an XOR operation on input sequences {m(p?1), m(p?2), . . . , m(0)} in a current period in sequence corresponding to output upper bits of the previous period of a register separately, outputting operation results as selection signals to a selector, selecting P constant-multinomials {xr<<0) mod g(x), (xr<<1) mod g(x), . . . , (xr<<(p?1)) mod g(x)} with 0 separately in sequence, shifting the selection results and the output of the previous period of the register in P bits towards the upper bits and outputting the selection results, summing the selection results and outputting the sum to the register to serve as an output of the current period of the register; the above steps are repeated specific times to obtain final code output.

Abstract: Techniques are disclosed for message retransmission. In one embodiment, an agent in a distributed system that receives and/or relays messages from a master node identifies messages that have not been successfully delivered, and adds a stub for each such message to a message queue. The agent then requests retransmission of missing messages in the message queue and sets flags associated with the message stubs to indicate that retransmission requests have been sent. If one (or more) of the messages cannot be retransmitted, the master node sends acknowledgment message(s) notifying the agent of the master node's inability to retransmit the messages. The agent then resets the flags corresponding to those messages to indicate that retransmission request(s) need to be sent again.

Abstract: A method of decoding a non-binary Low Density Parity Check (LDPC) code is provided. The method includes a plurality of messages to perform hard decision for all messages except for one message, and combines the hard-decided values with the one message that is not hard-decided, to update a final output message.

Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.

Abstract: A plurality of data words are written into a TCAM; each has binary digits and don't-care digits. Contemporaneously, for each of the words: a first checksum is calculated on the binary digits; and the following are stored in a corresponding portion of a RAM: an identifier of the binary digits and the first checksum. The ternary content-addressable memory is queried with an input word. Upon the querying yielding a match, further steps include retrieving, from the random-access memory, corresponding values of the identifier of the binary digits and the first checksum; computing a second checksum on the input word, using the identifier of the binary digits; and if the second and first checksums are not equal, determining in real time that the match is a false positive.

Abstract: Analyzing data is disclosed. Error events are tracked. The error events are classified based on a number of errors included in each event. A desired level of error event to be able to be corrected in order to maintain an acceptable rate of uncorrected errors is determined. A redundancy level is selected so that new error events corresponding to the desired level of error event or a lower level of error event are corrected.

Abstract: According to an embodiment, a row decoder to perform row decoding by using, as row soft input information, a row received word read as soft determination information from a non-volatile memory and to calculate row extrinsic information and a column decoder to perform column decoding by using column soft input information, which is a result of adding of the row extrinsic information to a column received word read as soft determination information from the non-volatile memory, and to calculate column extrinsic information are included. The row decoder includes a first decoder for first decoding, a second decoder for second decoding a decoding method of which is different from that of the first decoding, and a selection unit to select a decoded result based on accuracy of a decoded result of the first decoding and that of a decoded result of the second decoding and to calculate the row extrinsic information.

Abstract: High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed.

Abstract: According to one embodiment, a controller controls a nonvolatile memory stores data page by page. The controller is configured to extract, from a first data sequence shorter than the data length of a page, a second data sequence shorter than the first data sequence, to refer to the difference between threshold voltages corresponding to two data included in the second data sequence, to convert the second data sequence into a third data sequence longer than the second data sequence, and to control the percentage of the length of an error correction code added to the third data sequence.

Abstract: The present disclosure is directed to fast approximate conflict detection. A device may comprise, for example, a memory, a processor and a fast conflict detection module (FCDM) to cause the processor to perform fast conflict detection. The FCDM may cause the processor to read a first and second vector from memory, and to then generate summaries based on the first and second vectors. The summaries may be, for example, shortened versions of write and read addresses in the first and second vectors. The FCDM may then cause the processor to distribute the summaries into first and second summary vectors, and may then determine potential conflicts between the first and second vectors by comparing the first and second summary vectors. The summaries may be distributed into the first and second summary vectors in a manner allowing all of the summaries to be compared to each other in one vector comparison transaction.

Abstract: Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q?1 elements corresponding, respectively, to q?1 level-thresholds which partition the signal level vector into q segments, is then defined. The q?1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

Abstract: A memory system or flash memory device may include mechanism for handling power loss with a dual programming architecture. The state of primary and secondary blocks may be reconstructed to a state immediately preceding a power loss. The reconstruction may include comparing error correction code (ECC) headers of blocks to recreate a block exchange with fewer control updates. The comparison can be used to identify a primary and secondary block. The header may identify a particular stream, identify a free block, identify a release block, and other information.

Abstract: A method for transmitting data over an optical super-channel partitions the data unequally into a set of data streams for transmission over the set of sub-channels of the super-channel, such that a size of a first data stream for transmission over a first sub-channel is different than a size of a second data stream of the data for transmission over a second sub-channel. The method encodes each data stream of the data with an error correction code (ECC) having different ECC rates to produce a set of encoded data streams and transmits concurrently the set of encoded data streams over the set of sub-channels of the super-channel. Accordingly, the method uses an adaptive ECC for optical super-channels, such that a first ECC rate for encoding the first data stream is different than a second ECC rate for encoding the second data stream.

Abstract: A system and methodology for exploiting channel correlation in time and/or frequency to reduce CQI feedback in wireless communications systems. By compressing CQI feedback at the receiver to reduce redundancy in CQI feedback information that results from the channel correlation, the average feedback rate is reduced. Redundancy in time may be removed from the CQI feedback by monitoring variations of the CQI information in time at the receiver so that a codebook index for a given reporting instance is communicated to the transmitter only if it differs from the codebook index for the previous reporting instance. Otherwise, no feedback is performed.

Abstract: The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.

Abstract: A method and an apparatus for encoding and decoding in an electronic device are provided. In a decoding method, at least one parity symbol is received. A Cauchy matrix is generated using the at least one parity symbol. A Cauchy submatrix is configured from the Cauchy matrix based on the number of at least one lost data symbol and an inverse matrix of the Cauchy submatrix is calculated. At least one parity symbol corresponding to the at least one lost data symbol is updated. The at least one lost data symbol is recovered using the updated at least one parity symbol.