Abstract: A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. For each error signature, a priority of the mapping is determined by the signature type the respective error signature has been assigned to.

Abstract: The test circuitry according to various aspects of the presently disclosed techniques comprises: low-toggling pseudo-random test pattern generation circuitry, wherein the low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator; scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry; background chains configurable to shift in a background test pattern; and weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.

Abstract: A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a predetermined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the predetermined column among one or more column(s) of the parity check matrix.

Abstract: The present invention provides a design framework that is used to develop new types of constrained turbo block convolutional (CTBC) codes that have higher performance than was previously attainable. The design framework is applied to design both random and deterministic constrained interleavers. Vectorizable deterministic constrained interleavers are developed and used to design parallel architectures for real time SISO decoding of CTBC codes. A new signal mapping technique called constrained interleaved coded modulation (CICM) is also developed. CICM is then used to develop rate matching, spatial modulation, and MIMO modulation subsystems to be used with CTBC codes and other types of codes. By way of example, embodiments are primarily provided for improved 5G LTE and optical transport network (OTN) communication systems.

Abstract: Systems and methods are provided for decoding a codeword having a first codeword length using a decoding system. The systems and methods include receiving a vector corresponding to the codeword at the decoding system, wherein the decoding system comprises a first decoder and a second decoder, the first decoder is available to concurrently process codewords up to the first codeword length, and the second decoder is available to concurrently process codewords up to a second codeword length. The systems and methods further include determining that the received vector is to be decoded using the second decoder, partitioning the received vector of the first codeword length into a plurality of segments having a size no larger than the second codeword length, and decoding the plurality of segments using the second decoder.

Abstract: A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.

Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

Abstract: A network device including a matrix generating module, an encoding module and a transceiver. The matrix generating module is configured to generate or access a code base matrix, wherein the code base matrix has a corresponding code rate of 7/8. The matrix generating module is also configured to, based on the code base matrix, generate a resultant matrix of a low-density parity-check code. The resultant matrix includes sub-matrices. Each of the sub-matrices is generated based on a respective element in the code base matrix. The resultant matrix has a code length of 648 or 1296. The encoding module is configured to encode data based on the resultant matrix. The transceiver is configured to transmit the encoded data.

Abstract: A method of conditioning payload data includes providing a processor and receiving a packet comprising payload data, a first error code, and a second error code. The method also includes computing, using the processor, a first recalculated error code and determining a difference between the first error code and the first recalculated error code. The method further includes modifying the payload data in response to determining the difference.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: A method and electronic device for encoding data are provided. The method includes acquiring sets xj (j=1 . . . k) and yi (i=1 . . . p) in generating a Generator Cauchy Matrix, wherein k denotes a number of information symbols, and p denotes a number of parity symbols, generating a matrix A1 using the sets xj and yi, wherein elements of the matrix A1 are obtained by 1 x j + y i and have weight of Galois field, and the matrix A1 has a size of P×K, generating a set K, wherein all elements of the set K are not included in the sets xj and yi, updating the set xj by changing at least one element of the set xj for an element of the set K, updating the set yi by changing at least one element of the set yi for the set K element, generating the Generator Cauchy Matrix using the updated sets xj and yi, and encoding data including the information symbols and parity symbols using the Generator Cauchy Matrix.

Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.

Abstract: Techniques herein support enhanced multi-rate encoding and decoding of signals in multiple formats. In one embodiment, input data is received at a first device at one of a plurality of data rates. Encoder units are activated to produce streams of encoded input data. The encoder units are configured to operate at the same data rate. Differential encoding operations are performed to produce an encoded output stream. The encoded output stream is modulated for transmission to a second device. In another embodiment, a first device receives an encoded data stream that is transmitted from a second device. The modulated data stream includes encoded data at one of a plurality of data rates. Differential decoding is performed on the encoded data by activating one or more of a plurality of decoder units, where each of the plurality of decoder units is configured to operate at the same rate.

Abstract: Systems and methods are provided for decoding a codeword of a low density parity check (LDPC) code. The systems and methods may include receiving a vector corresponding to the codeword encoded with a parity check matrix, and processing a first portion of the received vector with a first portion of the parity check matrix to obtain a decoding estimate of a first portion of the codeword. The systems and methods may further include processing the decoding estimate of the first portion of the codeword with a second portion of the parity check matrix to obtain an intermediate vector, and processing a second portion of the received vector with a third portion of the parity check matrix and the intermediate vector to obtain a decoding estimate of a second portion of the codeword.

Abstract: A method begins by a processing module of a dispersed storage network (DSN) concatenating a plurality of independent data objects into a concatenated data object and performing a dispersed storage error encoding function on the concatenated data object to produce a set of data-based encoded data slices and a set of redundancy-based encoded data slices. The method continues with the processing module outputting the set of data-based encoded data slices to a first set of storage units for storage and outputting the set of redundancy-based encoded data slices to a second set of storage units for storage.

Abstract: A data detector includes a branch metric calculator operable to calculate branch metrics for transitions between states in a trellis for the data detector, and a pruning circuit operable to prune prohibited states from the trellis. The states in the trellis comprise basic states and extended states, where the extended states have a greater number of bits than the basic states.

Abstract: A decoding device includes a decoding unit that iteratively obtains a decoded bit stream corresponding to an information bit stream of one block, and an error detection unit that divides the decoded bit stream into a plurality of sub-blocks, acquires a plurality of partial remainders respectively corresponding to the sub-blocks, and determines whether an error occurs in the decoded bit stream based on a total remainder in which the partial remainders are added, wherein the error detection unit, of the sub-blocks, acquires a first partial remainder corresponding to a first sub-block including bits in which values are different between a previous decoded bit stream and a current decoded bit stream, and determines whether the error occurs in the current decoded bit stream based on a current total remainder obtained by adding the acquired first partial remainder to a previous total remainder.

Abstract: Correction of errors within over-the-air signaling is contemplated. The error correction may include correcting over-the-air signaling used to facilitate transmitting content, broadcast television, etc. according to error correction data transmitted separately from the over-the-air signaling. A receiver may be configured to process the over-the-air signaling according to the error correction data so as to facilitate the contemplated error correction.

Abstract: A device for correcting an initial binary word affected by an error in 1 or 2 bits and arising from a corrector code endowed with a minimum Hamming distance of 3 or 4, comprises first means for correcting an error of 1 bit and for detecting an error of more than 1 bit in the initial word and second means for correcting an error of 1 bit in a word arising from an inversion module, able to receive a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, said inversion module being configured to invert the bits of the initial word which suffer the low confidence level, and a multiplexer with at least two inputs which is driven by the means for detecting an error of more than 1 bit in the initial word, said multiplexer being fed on a first input by the output of the first correction means and on a second input by the output of the second correction means.

Abstract: A method of decoding data encoded with a polar code and devices that encode data with a polar code. A received word of polar encoded data is decoded following several distinct decoding paths to generate a list of codeword candidates. The decoding paths are successively duplicated and selectively pruned to generate a list of potential decoding paths. A single decoding path among the list of potential decoding paths is selected as the output and a single candidate codeword is thereby identified. In another preferred embodiment, the polar encoded data includes redundancy values in its unfrozen bits. The redundancy values aid the selection of the single decoding path. A preferred device of the invention is a cellular network device, (e.g., a handset) that conducts decoding in accordance with the methods of the invention.