Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.

Abstract: Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment.

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. An edge region exposed by the first electrode and the second electrode is covered by at least one of a healing layer or a block layer.

Abstract: A storage element including a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer being changed through injection of spin polarized electrons by passing a current in the lamination direction, so as to record information in the storage layer, wherein a spin barrier layer configured to restrain diffusion of the spin polarized electrons is provided on the side, opposite to the pinned magnetization layer, of the storage layer; and the spin barrier layer includes at least one material selected from the group composing of oxides, nitrides, and fluorides.

Abstract: Methods of forming variable-resistance devices include forming a variable-resistance layer between a first terminal and a second terminal from a material that varies in resistance based on an oxygen concentration. An electrolyte layer is formed over the variable-resistance layer from a material that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. A conductive gate layer is formed over the electrolyte layer.

Abstract: A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped conductor on a back side of the substrate is provided. The device further includes a first through-substrate via (TSV) electrically connecting a first end of the substantially spiral-shaped conductor to a first one of the plurality of circuit elements, and a second TSV electrically connecting a second end of the substantially spiral-shaped conductor to a second one of the plurality of circuit elements. The device may be a package further including a second die having a front side on which is disposed a second substantially spiral-shaped conductor. The front side of the second die is disposed facing the back side of the substrate, such that the first and second substantially spiral-shaped conductors are configured to wirelessly communicate.

Abstract: A method of manufacturing a nitride semiconductor light-emitting element configured to emit deep ultraviolet light includes: providing a semiconductor structure comprising: an n-side semiconductor layer comprising an n-side contact layer comprising aluminum, gallium, and nitrogen, a p-side semiconductor layer, and an active layer between the n-side semiconductor layer and the p-side semiconductor layer; forming an n-side electrode, which comprises forming, successively from an n-side contact layer side: a first layer located above the n-side contact layer and comprising a titanium layer, a second layer located above the first layer and comprising a silicon-containing aluminum alloy layer, and a third layer located above the second layer and comprising a tantalum layer and/or a tungsten layer; and heating the n-side electrode.

Abstract: A high-temperature silicon carbide device, along with an integrated circuit including the device and method of fabricating the device are described. For example, the method includes forming one of a source region and a drain region of a silicon carbide metal-oxide-semiconductor device. The method may include forming a gate structure adjacent to either one of the source region and the drain region. The gate structure may include an insulating layer. The method may further include forming the insulating layer with a first growth step performed in a pure oxygen environment and with a second growth step performed in a nitrous oxide environment.

Abstract: A pressure sensor device includes a semiconductor die having a die surface that includes a pressure sensitive area; and a bond wire bonded to a first peripheral region of the die surface and extends over the die surface to a second peripheral region of the die surface, wherein the pressure sensitive area is interposed between the second peripheral region and the first peripheral region, wherein the bond wire comprises a crossing portion that overlaps an area of the die surface, and wherein the crossing portion extends over the pressure sensitive area that is interposed between the first and the second peripheral regions.

Abstract: An integrated circuit includes a substrate, first and second n-type wells and a p-type well over the substrate, a first row of cells over the p-type well and the first n-type well, and a second row of cells over the p-type well and the second n-type well. The first and the second n-type wells sandwich the p-type well from a top view. The first row of cells include gate-all-around (GAA) nanosheet (NS) cells and GAA nanowire (NW) cells. The second row of cells include GAA NS cells and GAA NW cells. Each GAA NS cell includes an NMOS GAA NS transistor and a PMOS GAA NS transistor, each GAA NW cell includes an NMOS GAA NW transistor and a PMOS GAA NW transistor. Each transistor includes vertically stacked multiple first channels. The first channels of the GAA NS transistors are wider than the first channels of the GAA NW transistors.

Abstract: Disclosed is a magnetic memory device including a first magnetic pattern that extends in a first direction and has a magnetization direction fixed in one direction, and a plurality of second magnetic patterns that extend across the first magnetic pattern. The second magnetic patterns extend in a second direction intersecting the first direction and are spaced apart from each other in the first direction. Each of the second magnetic patterns includes a plurality of magnetic domains that are spaced apart from each other in the second direction.

Abstract: A SiC integrated circuit structure which allows multiple power MOSFETs or LDMOSs to exist in the same piece of semiconductor substrate and still function as individual devices which form the components of a given circuit architecture, for example, and not by limitation, in a half-bridge module. In one example, a deep isolation trench is etched into the silicon carbide substrate surrounding each individual LDMOS device. The trench is filled with an insulating material. The depth of the trench may be deeper than the thickness of an epitaxial layer to ensure electrical isolation between the individual epitaxial layer regions housing the individual LDMOSs. The width of the trench may be selected to withstand the potential difference between the bias levels of the body regions of neighboring power LDMOS devices.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: A method for forming a fin field effect transistor (FinFET) device structure and method for forming the same are provided. The method includes providing a substrate, and forming a fin structure on the substrate. The method also includes forming a protection layer on the sidewalls of the fin structure, and forming a dielectric layer on the fin structure and the protection layer. The method further includes removing a portion of the dielectric layer until a portion of the protection layer is exposed, and removing the exposed portion of the protection layer, such that the sidewalls of a lower portion of the fin structure are covered by the protection layer, and the sidewalls of an upper portion of the fin structure are not covered by the protection layer.

Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

Abstract: A light emitting structure has quantum wells grown on a coalesced substrate stemming from nanocolumns. The crystal structure is very low in defects and efficiency of light production is good. By growing the nanocolumns at a lower temperature, the quantum well structure is better matched to the coalesced substrate and efficiency is improved.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: A method of forming a micro electro mechanical system (MEMS) assembly comprises providing a substrate having an electrically conductive layer disposed thereon. The method also comprises depositing, on the substrate over the electrically conductive layer, a bonding material having an elastic modulus of less than 500 MPa so as to form a bond layer. The bond layer is completely cured, and a MEMS die is attached to the completely cured bond layer.

Abstract: The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.